Lecture 9: Combinational Circuit Design

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Transcription:

Lecture 9: Combinational Circuit Design

Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates Skewed Gates Best P/N ratio 0: Combinational Circuits CMOS VLSI Design 4th Ed.

Example module mux(input s, d0, d, output y); assign y = s? d : d0; endmodule ) Sketch a design using ND, OR, and NOT gates. D0 S D S 0: Combinational Circuits CMOS VLSI Design 4th Ed. 3

Example ) Sketch a design using NND, NOR, and NOT gates. ssume ~S is available. D0 S D S 0: Combinational Circuits CMOS VLSI Design 4th Ed. 4

Bubble Pushing Start with network of ND / OR gates Convert to NND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan s Law (a) (b) (c) D (d) 0: Combinational Circuits CMOS VLSI Design 4th Ed. 5

Example 3 3) Sketch a design using one compound gate and one NOT gate. ssume ~S is available. D0 S D S 0: Combinational Circuits CMOS VLSI Design 4th Ed. 6

Compound Gates Logical Effort of compound gates = = ib+ C = B+ C D i i i( ) = B+ C + DiE 0: Combinational Circuits CMOS VLSI Design 4th Ed. 7

Example 4 The multiplexer has a maximum input capacitance of 6 units on each input. It must drive a load of 60 units. Estimate the delay of the two designs. H = 60 / 6 = 0 B = N = D0 S D S P = + = 4 G = (4/3) i(4/3) = 6/9 F = GBH = 60 / 9 ˆ N f = F = 4. D = Nfˆ + P =.4τ D0 S D S P = 4+ = 5 G = (6/3) i() = F = GBH = 0 ˆ N f = F = 4.5 D = Nfˆ + P = 4τ 0: Combinational Circuits CMOS VLSI Design 4th Ed. 8

Example 5 nnotate your designs with transistor sizes that achieve this delay. 8 8 8 8 8 8 8 8 5 5 5 5 0 0 6 6 6 60 * (4/3) / 4. = 50 6 60 * / 4.5 = 36 6 0 0 6 4 0: Combinational Circuits CMOS VLSI Design 4th Ed. 9

Input Order Our parasitic delay model was too simple Calculate parasitic delay for falling If arrives latest? τ If B arrives latest?.33τ B x 6C C 0: Combinational Circuits CMOS VLSI Design 4th Ed. 0

Inner & Outer Inputs Inner input is closest to output () Outer input is closest to rail (B) If input arrival time is known Connect latest input to inner terminal 0: Combinational Circuits CMOS VLSI Design 4th Ed.

symmetric Gates symmetric gates favor one input over another Ex: suppose input of a NND gate is most critical Use smaller transistor on (less capacitance) Boost size of noncritical input reset So total resistance is same g = 0/9 g B = 4/3 reset 4 g total = g + g B = 8/9 symmetric gate approaches g = on critical input But total logical effort goes up 0: Combinational Circuits CMOS VLSI Design 4th Ed.

Symmetric Gates Inputs can be made perfectly symmetric B 0: Combinational Circuits CMOS VLSI Design 4th Ed. 3

Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) / / Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u =.5 / 3 = 5/6 g d =.5 /.5 = 5/3 0: Combinational Circuits CMOS VLSI Design 4th Ed. 4

HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nmos) LO-skew gates favor falling output (small pmos) Logical effort is smaller for favored direction But larger for the other direction 0: Combinational Circuits CMOS VLSI Design 4th Ed. 5

Catalog of Skewed Gates Inverter NND NOR unskewed g u = g d = g avg = B g u = 4/3 g d = 4/3 g avg = 4/3 B 4 4 g u = 5/3 g d = 5/3 g avg = 5/3 HI-skew / g u = 5/6 g d = 5/3 g avg = 5/4 B g u = g d = g avg = 3/ B / 4 4 / g u = 3/ g d = 3 g avg = 9/4 LO-skew g u = 4/3 g d = /3 g avg = B g u = g d = g avg = 3/ B g u = g d = g avg = 3/ 0: Combinational Circuits CMOS VLSI Design 4th Ed. 6

symmetric Skew Combine asymmetric and skewed gates Downsize noncritical transistor on unimportant input Reduces parasitic delay for critical input reset reset 4/3 4 0: Combinational Circuits CMOS VLSI Design 4th Ed. 7

Best P/N Ratio We have selected P/N ratio for unit rise and fall resistance (μ = -3 for an inverter). lternative: choose ratio for least average delay Ex: inverter Delay driving identical inverter P t pdf = (P+) t pdr = (P+)(μ/P) t pd = (P+)(+μ/P)/ = (P + + μ + μ/p)/ dt pd / dp = (- μ/p )/ = 0 Least delay for P = μ 0: Combinational Circuits CMOS VLSI Design 4th Ed. 8

P/N Ratios In general, best P/N ratio is sqrt of equal delay ratio. Only improves average delay slightly for inverters But significantly decreases area and power Inverter NND NOR fastest.44 P/N ratio g u =.5 g d = 0.8 g avg = 0.98 B g u = 4/3 g d = 4/3 g avg = 4/3 B g u = g d = g avg = 3/ 0: Combinational Circuits CMOS VLSI Design 4th Ed. 9

Observations For speed: NND vs. NOR Many simple stages vs. fewer high fan-in stages Latest-arriving input For area and power: Many simple stages vs. fewer high fan-in stages 0: Combinational Circuits CMOS VLSI Design 4th Ed. 0

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