lick here for production status of specific part numbers. MX0 Evaluation System Evaluates: MX0 General escription The MX0 evaluation system offers a compact development platform that provides access to all the features of the MX0 in a tiny, easy to use board. MXPIO-based debug adapter comes attached to the main board. It can be snapped free when programming is complete. The debug module supports an optional 0-pin rm ortex debug connector for PLink functionality. ombined measurements are 0.in x.in, while the main board alone measures 0.in x 0.in. External connections terminate in a dual-row header footprint compatible with both thru-hole and SMT applications. This board provides a powerful processing subsystem in a very small space that can be easily integrated into a variety of applications. Kit ontents MX0 EVSYS board US to Micro cable Features MX0 Microcontroller rm ortex-mf, MHz K Flash Memory K SRM K Instruction ache Two SPIs Two Is Two URTs GPIOs IP reakout oard 00mil Pitch ual Inline Pin Headers readboard ompatible Integrated Peripherals Red Indicator LE User Pushbutton MXPIO-ased ebug dapter MSIS-P SW ebugger Virtual URT onsole Ordering Information appears at end of data sheet. MX0 EV System Photo rm and ortex are registered trademarks of rm Limited (or its subsidiaries) in the US and/or elsewhere. -000; Rev ; /
MX0 Evaluation System Evaluates: MX0 rd nd st NME NME st nd rd TS SK P0_ P0_0 MISO TX RTS SSEL P0_ P0_ MOSI RX TX MISO P0_ P0_ MOSI RX TMR SSEL S P0_ P0_ SK TS TX KL SK SL P0_ P0_ SSEL RTS RX RX MOSI SWLK P0_ P0_ SL SWIO TX MISO SWIO P0_0 P0_ S SWLK VORE GN Figure. Pinout iagram Quick Start To begin using the MX0 EV system, follow these steps: ) Use jumper JP to select desired target V. ) onnect the EVSYS board to the computer using the included micro US cable. ) Follow the instructions in the MX0 EV system software user s guide. etailed escription of Hardware (or Software) The MX0 EV system board is a compact breakout board designed to make developing with the MX0 quick and easy. In addition to making all the GPIOs accessible at 00mil pitch headers, it also includes key components such as decoupling capacitors and a crystal for the RT. pushbutton, LE, and debug adapter are also included. The two 00mil pitch headers are oriented in parallel so that this board can be inserted into a standard solderless breadboard. Power Supply The MX0 only needs a single supply between.v and.v to operate. The primary power input for this EV kit is the VIO pin at header J pin. Power can also be applied through the debug adapter (JP selects voltage). The MX0 includes an internal LO for the core supply. This LO can be disabled so that a more efficient external regulator can be used. The EV kit provides access to VORE at header JH pin. VIO and VORE are each decoupled with µf capacitors. Programming and ebugging The MX0 EV kit integrates a MXPIObased debugger. The debugger provides power to the MX0 and is designed to be removed from the system when programming is finalized. It can be reattached by restoring the electrical connections between JH and JH. Maxim Integrated
MX0 Evaluation System Evaluates: MX0 onsole URT URT Tx and Rx signals at port P0.0 and P0. are connected to the programming and debug header JH pins and through kω resistors. This provides a convenient way to communicate with a P though the virtual serial port available in Maxim s MSIS-P debug adapter. The series resistors allow for these signals to be overdriven by other circuits without modifying the board. Pushbutton pushbutton is connected to GPIO P0. for general user input. It is connected through a series resistor to protect against contention if this I/O is being used for other purposes. Indicator LE red LE is connected to GPIO P0. for general user indication. It is connected with a MOSFET buffer so that it does not provide a significant load when used for other purposes. locking The I operates from a system clock that can be selected from one of three on-chip oscillators from khz to MHz. The external.khz crystal, Y, provides the RT with an accurate time base and is also used to calibrate the internal clock. Table. JH Header Pinout PIN NME LTERNTE FUNTION LTERNTE FUNTION LTERNTE FUNTION P0. SPI_SK URT_TS P0. SPI_SS0 URT_RTS P0. SPI0_MISO URT0_TX P0. I_S SPI_SS0 TIMER_TMR0 P0. I_SL SPI_SK KL P0. SWLK SPI_MOSI URT_RX P0.0 SWIO SPI_MISO URT_TX GN Table. JH Header Pinout PIN NME LTERNTE FUNTION LTERNTE FUNTION LTERNTE FUNTION P0.0 SPI_MISO URT_TX P0. SPI_MOSI URT_RX P0. SPI0_MOSI URT0_RX P0. SPI0_SK URT0_TS URT_TX P0. SPI0_SS0 URT0_RTS URT_RX P0. I0_SL SWIO P0. I0_S SWLK VORE VIO Ordering Information PRT MX0-EVSYS# #enotes RoHS compliance. TYPE EV System Maxim Integrated
MX0 Evaluation System Evaluates: MX0 MX0 EV System ill of Materials QTY PRT VLUE OM ESRIPTION MNUFTURER PN MNUFTURER,,,,,,0,,, uf P ER UF.V XR GRMR0J0KE Murata,,,.uF P ER.uF 0V 0% XR 00 00KPTU Kemet 0nF P ER 0000PF V 0% XR GRMR0K0 Murata Electronics North merica 00nF P ER 0.UF 0V 0% XR GRMR0K0 Murata 00nF P ER 0.UF.V 0% XR 00 GRM0R0J0KE Murata SML-LX00SIUPGUS LE RG LER 00 SM SML-LX00SIUPGUS Lumex Opto/omponents Inc. RE LE RE IFFUSE 00 SM SML-LX00SRW-TR Lumex Opto/omponents Inc. J MIRO US R/ ONN RPT POS MIRO US R/ -000 Molex J MXP MXP_POGO_PIN L PLUG-OF-NILS 0-PIN T00-I-NL Tag-onnect LL J P TP P US TP.MM SMT P J 0P ORTEX EUG ONN HEER 0POS UL.0" SM FTSH-0-0-F-V-K Samtec JH NI NI ON P LS0MIL SMT 0XP REKWY JH NI NI ON P LS0MIL SMT 0XP REKWY JH,JH P x ONN HEER.00 SINGL STR POS PE0SN Sullins JP P JUMPER ONN HEER.00 SINGL STR POS PE0SN Sullins P P Q MP0UF- MOSFET P-H 0V 0. X-FN00 MP0UF- iodes Incorporated Q SS0N MOSFET N-H 0V. SOT SS0N H Infineon Technologies R,R.K RES SM.K OHM % /0W ERJ-RKF0X Panasonic R.K RES SM.K OHM % /0W ERJ-RKF0X Panasonic Electronic omponents R,R0,R,R K RES K OHM /0W % SM ERJ-RKF00X Panasonic R,R 0 RES SM 0 OHM % /0W ERJ-RKF0R0X Panasonic R 00K RES SM 00K OHM % /0W ERJ-RKF00X Panasonic R,R,R 0K RES SM 0K OHM % /W RFR-00KL Yageo R,R RES SM OHM % /0W ERJ-RKF0X Panasonic Electronic omponents R,R 0 RES 0.0 OHM /0W JUMP SM ERJ-GE0R00X Panasonic R 0K RES SM 0K OHM % /0W ERJ-RKF0X Panasonic R,R0 0 RES 0.0 OHM /0W JUMP 00 SM ERJ-GN0R00 Panasonic SH,SH,SH NI NI NET SHORT MIL LINE SW,SW U-000P SWITH TTILE SPST-NO 0.0 V U-000P Omron Electronics U MXELT+T I REG LINER.V 0M UFN MXELT+T Maxim Integrated U MXIWY+T I MU IT K FLSH WLP MXIWY+T Maxim Integrated U MXELT+T I REG LINER.V 0M UFN MXELT+T Maxim Integrated U MX0T+ I REG LO LINER J. TFN MX0T+ Maxim Integrated U MX0GTP+ MX0GTP+ 0P TQFN MX0GTP+ Maxim Integrated U SE0R+T I EEPROM IT WIRE SOT- SE0R+T Maxim Integrated U MX0ELT+T ES PROTET H -UFN MX0ELT+ Maxim Integrated U MXEWL+T I SWITH NLOG PT -WLP MXEWL+T Maxim Integrated Y,Y.KHz RYSTL.0KHZ PF SM ES-.---TR EX-_00x0 Maxim Integrated
MX0 Evaluation System Evaluates: MX0 MX0 EV System Schematic Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. opyright 0 - Maxim Integrated Title MX0 EVSYS - lock iagram Size ocument Number Rev S-00 x Friday, July 0, 0 ate: Sheet of Maxim Integrated
MX0 Evaluation System Evaluates: MX0 MX0 EV System Schematic (continued) J MIRO US R/ -000 VUS M P I GN GN_ GN_ GN_ GN_ J P TP P.MM P SW PROG FW UPTE P _P_ 0 ohm differential traces uf U V GN N_ N_ IO IO MX0ELT+T P x. ufn _M _P uf uf.uf 00 U MXELT+T IN OUT SHN N GN N P.X.0 UFN U MXELT+T IN OUT SHN N GN N P.X.0 UFN U MX0T+ IN OUT GN YP EP EN OUTS SEL SEL P X TFN uf uf 0nF V V V JP TRGET V X (0." LS) V V.uF 00 HR_W SW_W _P0_0 _P0 P0 P0 P0 P _M _G_SRST _G_SW _G_SW SW_VIO HR_TGT_TX HR_TGT_RX HR_LK HR_IO HR_RST S_ SL_ G_SRST G_SW G_SW U MXIWY+T IN0 IN IN IN P0_0 P0_ P0_ P0_ P0_ P0_ P0_ P0_ E P_0 P_ E P_ E P_ F P_ F P_ F P_ P_ E E P M S TK TMS TO TI KOUT G P_0 G P_ G P_ F P_ G P_ E P_ F P_ G P_ E P_0 F P_ G P_ P_ P_ G P_ F P_ G P_ G P_0 E P_ F P_ F P_ P_ P_ P_ P_ V E V VIOH G_RX G_TX IOH_W_EN SW_IP_SEL R_LE G_LE _LE P SW_TGT_TX SW_TGT_RX SW_LK SW_IO SW_RST OWM_IO OWM_PUPEN _P_0 _P P P P P P P P_0 _P P P P P_0 _P_ V V VIOH Y.KHz KIN VSS VSS VSS VRT VIO V V SML-LX00SIUPGUS P WLP uf uf 0 uf uf uf V OM RE K R.K R_LE _P_ LUE K GREEN K R.K R K _LE G_LE _P P_ V J SW/MXP T00-I-NL _P P_ SML-LX00SIUPGUS _G_SW _G_SW G_SW G_SW 0 V RST SW I GN RX SW N GN TX G_SRST G_RX G_TX _G_SRST _P_0 _P_ MXP _P P_0 Q MP0UF- OWM_PUPEN G S R 00K OWM_IO VIOH R.K U MXEWL+T VIOH OM R 0 OM N N NO NO HR_W J 0P ORTEX EUG V SWIO/TMS GN SWLK/TK GN SWO/TO KEY N/TI 0 GN_ETET NRESET SW_IO SW_LK SW_TGT_TX SW_TGT_RX SW_RST _P P P_0 _P P P_ SW_IP_SEL V IOH_W_EN _P_ 0P (0.0") Shrouded SW_W P WLP GN 00nF 00 SW_VIO opyright 0 - Maxim Integrated Title MX0 EVSYS - US Programmer Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Size ocument Number Rev S-00 x Friday, July 0, 0 ate: Sheet of Maxim Integrated
MX0 Evaluation System Evaluates: MX0 MX0 EV System Schematic (continued) R U SE0R+T IO P0_0 P0_ P0_ P0_ P0_ P0_ P0_ P0_ P0_ P0_ P0_0 P0_ P0_ P0_ U MX0GTP+ P0.0/SWIO/SPI_MISO (IS_SI)/URT_TX KIN 0 P0./SWLK/SPI_MOSI (IS_SO)/URT_RX P0./I_SL/SPI_SK (IS_LK)/KL P0./I_S/SPI_SS0 (IS_LRLK)/TMR0 KOUT P0./SPI0_MISO/URT0_TX P0./SPI0_MOSI/URT0_RX P0./SPI0_SK/URT0_TS/URT_TX P0./SPI0_SS0/URT0_RTS/URT_RX P0./I0_SL/SWIO P0./I0_S/SWLK V P0.0/SPI_MISO (IS_SI)/URT_TX 0 P0./SPI_MOSI (IS_SO)/URT_RX VORE P0./SPI_SK (IS_LK)/URT_TS P0./SPI_SS0 (IS_LRLK)/URT_RTS VSS EP 0P x TQFN Y.KHz VORE uf R 0K 00nF uf R 0 HR_W N.. GN SOT- P _P0 P0_0 _P0 P0_ HR_TGT_RX HR_TGT_TX HR_IO HR_LK JH NI P EGE SMT JH NI P EGE SMT R0 K R K R 0 NI R 0 NI P0_ P0_0 P0_0 P0_ R R 0K 0K P0_ P0_ SW P0_ R K P0_ R Q SS0N G S R 0K RE 00 SH NET SHORT NI SH NET SHORT NI SH NET SHORT NI _P0_ HR_RST _P P_ R 0 00 R0 0 00 P0_ P0_ P0_0 P0_ P0_ P0_ P0_ P0_ P0_ VORE JH JH P0_ P0_ P0_ P0_ P0_ P0_ P0_0 P x P x Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. opyright 0 - Maxim Integrated Title MX0 EVSYS - MX0 Size ocument Number Rev S-00 x Wednesday, July, 0 ate: Sheet of Maxim Integrated
MX0 Evaluation System Evaluates: MX0 Revision History REVISION NUMER REVISION TE ESRIPTION PGES HNGE 0 / Initial release / Updated Ordering Information For pricing, delivery, and ordering information, please visit Maxim Integrated s online storefront at https:///en/storefront/storefront.html. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 0 Maxim Integrated Products, Inc.