igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002
Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-submicron effects Future trends
The iode B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol Mostly occurring as parasitic element in igital ICs
epletion Region p Charge ensity hole diffusion electron diffusion hole drift electron drift - ρ + n x istance (a) Current flow. (b) Charge density. Φ Φ 0 T Built-in potential N N A = ΦT ln 2 ni KT = = 26 mv at q 300K Electrical Field ξ x (c) Electric field. N A : acceptor concentrations N : donor concentrations n i : intrinsic carrier concentration Potential V ψ 0 -W 1 W 2 Zero-Bias x (d) Electrostatic potential.
iode Current eviation due to recombination
Forward Bias I I dnp, n _ dx p = qa n p0 = qa p W n p n p0 dn dx W 1 p e V Φ T 1 p n (W 2 ) L p I I dpn, p _ dx p = qa = qa p n p dp dx pn0 W W 2 n p n0 e V Φ T 1 p-region -W 1 0 W 2 I = I + p I n n-region x diffusion Typically avoided in igital ICs
Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The ominant Operation Mode
Models for Manual Analysis V + I = I S (e V /φt 1) V + + I V on (a) Ideal diode model (b) First-order diode model
Junction Capacitance Junction Capacitance ( ) 1 0 0 0 2 2 Φ + = Φ + = A A si j A A si j N N N N A C V N N N N q A Q ε ε
iffusion Capacitance τ T : mean transit time Small signal capacitance
Secondary Effects 0.1 I (A) 0 0.1 25.0 15.0 5.0 0 5.0 V (V) Avalanche Breakdown
iode Model R S + V - I C
SPICE Parameters
What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron
The MOS Transistor Polysilicon Aluminum
MOS Transistors - Types and Symbols G G S NMOS Enhancement NMOS S epletion G G B PMOS S Enhancement S NMOS with Bulk Contact
Threshold Voltage: Concept S - V GS + G n+ n+ n-channel p-substrate epletion Region B
The Threshold Voltage
The Body Effect V T T 0 + γ ( ) 2Φ + V Φ = V 2 F S B F 0.9 0.85 V T (V) 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 V SB forward bias V T decrease V SB reverse bias V T increase 0.4-2.5-2 -1.5-1 -0.5 0 V BS (V)
Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V I (A) 3 V S = V GS -V T Quadratic Relationship 2 VGS= 1.5 V 1 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V S (V)
Transistor in Linear V V GS G > V T > V T V < S V S _ sat V GS S G V S I n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions
Transistor in Saturation V GS G V S > V GS - V T S n+ - V GS - V T + n+ Pinch-off
Current-Voltage Relations Long-Channel evice
A model for manual analysis
Current-Voltage Relations The eep-submicron Era 2.5 x 10-4 2 Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V I (A) 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V S (V)
Velocity Saturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm)
Perspective I Long-channel device V GS = V Short-channel device V SAT V GS -V T V S
I versus V GS 6 x 10-4 2.5 x 10-4 5 4 quadratic 2 1.5 linear I (A) 3 I (A) 2 1 1 0 0 0.5 1 1.5 2 2.5 V GS (V) Long Channel 0.5 quadratic 0 0 0.5 1 1.5 2 2.5 V GS (V) Short Channel
I versus V S I (A) 6 x 10-4 5 4 3 2 VGS= 2.5 V Resistive Saturation VGS= 2.0 V V S = V GS -V T VGS= 1.5 V I (A) 2 1.5 1-4 2.5 x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V 0 0 0.5 1 1.5 2 2.5 V S (V) Long Channel 0 0 0.5 1 1.5 2 2.5 V S (V) Short Channel
A unified model for manual analysis G S B
Simple Model versus SPICE 2.5 x 10-4 V S =V SAT 2 1.5 Velocity Saturated I (A) 1 Linear 0.5 V SAT =V GT V S =V GT Saturated 0 0 0.5 1 1.5 2 2.5 V S (V)
A PMOS Transistor 0 x 10-4 VGS = -1.0V -0.2 VGS = -1.5V -0.4 I (A) -0.6 VGS = -2.0V Assume all variables negative! -0.8 VGS = -2.5V -1-2.5-2 -1.5-1 -0.5 0 V S (V)
Transistor Model for Manual Analysis
The Transistor as a Switch V GS V T S Ron I V GS = V R mid R 0 V /2 V V S
The Transistor as a Switch 7 x 105 6 5 R eq (Ohm) 4 3 2 1 0 0.5 1 1.5 2 2.5 V (V)
The Transistor as a Switch
MOS Capacitances ynamic Behavior
ynamic Behavior of MOS Transistor G C GS C G S C SB C GB C B B
The Gate Capacitance Polysilicon gate Source n + x d x d W rain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + Cross section
Gate Capacitance G G G S C GC C GC C GC S S Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off
Gate Capacitance WLC ox C GC WLC ox C GC 2WLC ox WLC ox 2 C GC B C GCS = C GC WLC ox 2 C GCS C GC 3 V GS 0 V S /(V GS -V T ) 1 Capacitance as a function of VGS (with VS = 0) Capacitance as a function of the degree of saturation
iffusion Capacitance Channel-stop implant N A 1 Side wall W Source N Bottom x j L S Side wall Substrate N A Channel
Junction Capacitance
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
Capacitances in 0.25 µm m CMOS process
The Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances
Threshold Variations V T V T Long-channel threshold Low V S threshold Threshold as a function of the length (for low V S ) L V S rain-induced barrier lowering (for low L)
Sub-Threshold Conduction 10-2 10-4 Linear The Slope Factor I ~ I 0 e qv nkt GS, n =1+ C C ox I (A) 10-6 10-8 Quadratic S is V GS for I 2 /I 1 =10 10-10 Exponential 10-12 V T 0 0.5 1 1.5 2 2.5 V GS (V) Typical values for S: 60.. 100 mv/decade
Sub-Threshold I vs VGS qvgs nkt I I0e 1 e qv = kt S V S from 0 to 0.5V
Sub-Threshold I vs VS I qvgs qv = nkt kt I e 0 1 e S ( 1+ λ V ) S V GS from 0 to 0.3V
Summary of MOSFET Operating Regions Strong Inversion V GS >V T Linear (Resistive) V S <V SAT Saturated (Constant Current) V S V SAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V S dependence
Parasitic Resistances G Polysilicon gate L rain contact V GS,eff S W R S R rain
Latch-up
Future Perspectives 25 nm FINFET MOS transistor