Digital Integrated ircuits YuZhuo Fu contact:fuyuzhuo@ic.sjtu.edu.cn Office location:47 room WeiDianZi building,no 800 Donghuan road,minhang amus Introduction Digital I
3.MOS Inverter Introduction Digital I
outline MOS at a glance MOS static behavior MOS dynamic behavior Power, Energy, and Energy Delay Persective tech. Digital I 3
MOS dynamic characteristic MOS caacitances mosaic MOS roagation delay Otimizing inverter sizing Digital I 4
ircuit Under Design V DD V DD M M4 V in V out V out M M3 This two-inverter circuit will be manufactured in a twin-well rocess. Digital I 5
MOS Inverter: Transient Resonse V DD t H = f(r on. ) = 0.69 R on V out V out ln(0.5) R on V DD 0.5 0.36 V in = V DD R on t Digital I 6
MOS caacitance mosaic Wire caacitance Junction(diffusion) caacitance Gate caacitance Most of them are nonlinear functions! Digital I 7
omuting the aacitances V DD V DD PMOS V DD V in gd M db V out g4 M4 V out In. m =l Out Metal M db w Interconnect g3 M3 Polysilicon Fanout NMOS GND Simlified Model V in V out Digital I 8
aacitance model GS GD GB SB DB GSO GDO GB Sdiff Ddiff GS GD S GS SB G GB GD DB D B Digital I 9
The Miller Effect D V gd V out V out D V V in D V gd M D V V in M A caacitor exeriencing identical but oosite voltage swings at both its terminals can be relaced by a caacitor to ground, whose value is two times the original value. Digital I 0
Diffusion caacitances eq = K eq j0 K eq = (V high -Φ - V m 0 low [(Φ )(- m) 0 - V high ) -m - (Φ 0 - V low ) -m ] Digital I Slide
Miller effect Digital I
omuting the aacitances J JSW ox (ff/um ) o (ff/um) j (ff/um ) mj Φ b (V) jsw (ff/um) Mjsw NMOS 6 0.3 0.5 0.9 0.8 0.44 0.9 PMOS 6 0.7.9 0.48 0.9 0. 0.3 0.9 Φbsw (V) DG0 W/ AD(um ) PD(um) AS(um ) PS(um) NMOS 3/ 9 5 9 5 PMOS 9/ 45 9 45 9 Digital I 3
omuting the aacitances PMOS V DD AD=4*4+3*=6+3=9λ PD=+4+4+4++=5λ In Out. m =l Metal Polysilicon NMOS GND Digital I Slide 4
omuting the aacitances Vhigh=-.5V,Vlow=-.5V[NMOS,{.5V->.5V} H] Bottom late:keqn(m=0.5,φ0=0.9)=0.57 Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.6 Vlow=0V,Vhigh=-.5V [NMOS,{0V->.5V}H] Bottom late:keqn(m=0.5,φ0=0.9)=0.79 Sidewall:Keqwn(m=0.44,Φ0=0.9)=0.8 Vhigh=-.5V,Vlow=0V [PMOS,{.5V->.5V}H] Bottom late:keq(m=0.48,φ0=0.9)=0.79 Sidewall:Keqw(m=0.3,Φ0=0.9)=0.86 Vhigh=-.5V,Vlow=-.5V [PMOS,{0V->.5V}H] Bottom late:keq(m=0.48,φ0=0.9)=0.59 Sidewall:Keqw(m=0.3,Φ0=0.9)=0.7 Digital I 5
omuting the aacitances caacitor exression Value(fF) (H->) gd GD0n*Wn 0.3 0.3 gd GD0*W 0.6 0.6 db KeqnADnJ+KeqwnPDnJSW 0.66 0.90 db KeqnADnJ+KeqwnPDnJSW.5.5 g3 (GD0n+GSOn)Wn+oxWnn 0.76 0.76 g4 (GD0+GSO)W+oxW.8.8 w 0. 0. 6. 6.0 Value(fF) (->H) Digital I 6
omuting it more simle by estimation Introduction Digital I Slide 7
aacitance Any two conductors searated by an insulator have caacitance Gate to channel caacitor is very imortant reates channel charge necessary for oeration Source and drain have caacitance to body Across reverse-biased diodes alled diffusion caacitance because it is associated with source/drain diffusion Digital I Slide 8
Gate aacitance Aroximate channel as connected to source gs = e ox W/t ox = ox W = ermicron W ermicron is tyically about ff/mm olysilicon gate W t ox n+ n+ -tye body SiO gate oxide (good insulator, e ox = 3.9e 0 ) Digital I Slide 9
Diffusion aacitance sb, db Undesirable, called arasitic caacitance aacitance deends on area and erimeter Use small diffusion nodes omarable to g for contacted diff ½ g for uncontacted Varies with rocess Digital I Slide 0
Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too comlicated for much hand analysis Simlification: treat transistor as resistor Relace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to redict current at any given time But good enough to redict R delay Digital I Slide
R Delay Model Use equivalent circuits for MOS transistors Ideal switch + caacitance and ON resistance Unit nmos has resistance R, caacitance Unit MOS has resistance R, caacitance aacitance roortional to width Resistance inversely roortional to width g d k s g d R/k k s k k g d k s g s k R/k k k d Digital I Slide
Reason of R I DSAT = k ' W (V GT V DSAT - V DSAT ) Digital I Slide 3
R Values aacitance = g = s = d = ff/mm of gate width Values similar across many rocesses Resistance R 6 KW*mm in 0.6um rocess Imroves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/ l) Or maybe mm wide device Doesn t matter as long as you are consistent Digital I Slide 4
Inverter Delay Estimate Estimate the delay of a fanout-of- inverter A Y Digital I Slide 5
Inverter Delay Estimate Estimate the delay of a fanout-of- inverter R A Y R Y Digital I Slide 6
Inverter Delay Estimate Estimate the delay of a fanout-of- inverter R A Y R Y R Digital I Slide 7
Inverter Delay Estimate Estimate the delay of a fanout-of- inverter R A Y R Y R d = 6R Digital I Slide 8
MOS dynamic characteristic MOS caacitances mosaic MOS roagation delay Otimizing inverter sizing Digital I 9
Inverter Transient Resonse 3.5.5 0.5 0-0.5 t H t f V in t H t (sec) 0 0.5.5.5 From simulation: t H = 39.9 sec and t r x 0-0 t H = 3.7 sec V DD =.5V 0.5mm W/ n =.5 W/ = 4.5 R eqn = 3 kw (.5) R eq = 3 kw ( 4.5) t H = 36 sec t H = 9 sec so t = 3.5 sec Digital I
Proagation delay: first order analysis Proagation delay model of R R I eq sat VO VOH v VOH / VO v v dv 3V DD 7 (- V v v I ( lv ) 4I 9 l ( W ) n v sat k ' n V DSAT n ( V DD -V T n DSAT V - n DSAT Assuming transistor as saturation n ) DD ) Digital I 3
Digital I 33 Proagation delay: first order analysis Proagation delay model of R DSAT DD eq H I V R t ) V (- 4 3 0.69* ) ln( DD l DSATn DD eqn H I V R t ) V (- 4 3 0.69* ) ln( DD l ) /) - ( '* * /) - ( '* * ( 0.5* )* *( * 0.69*0.75/ 0.69* n n n n DSAT GT DSAT DSAT GT DSAT n n DD dsat dsatn DD eq eqn H H V V V k W V V V k W V I I V R R t t t
Inverter Proagation Delay, Revisited To see how a designer can otimize the delay of a gate have to exand the R eq in the delay equation 5.5 5 4.5 4 3.5 3.5.5 0.8..4.6.8..4 t H = 0.69 R eqn = 0.69 (3/4 ( V DD )/I DSATn ) V DD (V) 0.5 / (W/ n k n V DSATn ) Digital I
Design techniques for minimized roagation delay Reduce Kee the drain diffusion areas as small as ossible Increase the W/ ratio of the transistor Increase V dd t H ( W ) n k 0.5* ' n V DSAT n ( lv DD ) Digital I 35
Design for Performance Reduce internal diffusion caacitance of the gate itself kee the drain diffusion as small as ossible interconnect caacitance fanout Increase W/ ratio of the transistor the most owerful and effective erformance otimization tool in the hands of the designer watch out for self-loading! when the intrinsic caacitance dominates the extrinsic load Increase VDD can trade-off energy for erformance increasing VDD above a certain level yields only very minimal imrovements Digital I
Define NMOS-to-PMOS ratio t t H H ln( ) R eq n ln( ) R eq ( W ) ( W ) ' n kn ' k DSAT n In order to create an inverter with a symmetrical roagate delays Also create symmetrical VT V V DSAT ( W ) ( W ) n R eq k ' R V k eq ' n V DSAT n DSAT ( V β =.4 which Rn=R! n VDSAT n ( VM VTn ) V VM VT DD ( W ) ( W ) n k k ' n ' V V DSAT DSAT n DSAT ) Digital I 37
t (sec) Which oint is otimal delay? 5 x 0-4.5 t H t H t H ln( ) R eq ( W ) ' k V DSAT t 4 t H ln( ) Req n ( W ) ' n kn V DSAT n 3.5 b = W /W n 3.5.5 3 3.5 4 4.5 5 b Digital I 38
Which oint is otimal delay? ( W b d n ) d ( W ) n g n V DD g w ( b )( d n gn V DD ) w V in gd M db V out g 4 M 4 V out M db w Interconnect g 3 M 3 t t H t H 0.345(( b )( ln d n (( b )( g n ) d w n ) R eq n g n ( ) ) b )( R Digital I 39 w eq n R eq b )
Which oint is otimal delay? t 0 b [ 0.345(( b )( d n gn b ) w ) R eq n ( )] b 0 b ( dn w gn ) 3 3 Vdd.5V 0.5 um.54 This r is different from before! It is the resistor rate of the NMOS and PMOS Digital I 40
Summary of ratio Beta=.6, we have minimum delay Beta=.4, we have equal delay t hl =t lh Beta=3.5, we have V M =V dd / Digital I 4
MOS dynamic characteristic MOS caacitances mosaic MOS roagation delay Otimizing inverter sizing Digital I 4
Increasing inverter erformance by sizing the NMOS and PMOS t 0.69R 0.69( R 0.69t ref eq ( int S)( S 0 0. 69t 0 iref ext S ) )( ext iref 0.69R ext eq S int iref ( ) If load ext int ) If no load S>>0 will eliminate the imact of any external load Intrinsic delay is indeendent of the sizing of the gate Digital I 43
t (sec) Device Sizing 3.8 x 0-3.6 (for fixed load) 3.4 3. 3.8.6 Examle 5.5 Self-loading effect: Intrinsic caacitances dominate.4. 4 6 8 0 4 S Digital I 44
Inverter hain In Out If is given: - How many stages are needed to minimize the delay? - How to size the inverters? Digital I 45
Inverter Delay Minimum length devices, =0.5mm, Assume that for W P = W N =W same ull-u and ull-down currents arox. equal resistances R N = R P arox. equal rise t H and fall t H delays Analyze as an R network R P R unit W W P unit W R N unit W unit R N R W W W Delay (D): t H = (ln ) R N t H = (ln ) R P W oad for the next stage: gin 3 unit W unit Digital I 46
Inverter with oad Delay R W R W oad ( ) t = k R W k is a constant, equal to 0.69 Assumtions: no load -> zero delay W unit = Digital I 47
Inverter with oad P = unit W Delay W int N = unit oad Delay = kr W ( int + ) = kr W int + kr W = Delay (Internal) + Delay (oad)= kr W int (+ / int ) Digital I 48
Delay Formula Delay ~ R W int t kr W int / t f / int 0 int = gin with f = / gin - effective fanout R = R unit /W ; int =W unit t 0 = 0.69R unit unit Digital I 49
Aly to Inverter hain In Out N t = t + t + + t N t t j ~ R unit unit gin, j gin, N i N gin, j t j t, 0, gin, N j gin, j j Digital I 50
Otimal Taering for Given N Delay equation has N - unknowns, gin, gin,n Minimize the delay, find N - artial derivatives Result: gin,j+ / gin,j = gin,j / gin,j- Size of each stage is the geometric mean of two neighbors gin, j gin, j gin, j each stage has the same effective fanout ( out / in ) each stage has the same delay Digital I 5
Otimum size for fixed Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: f N F f N F / gin, Minimum ath delay t Nt 0 N F / Digital I 5
Examle In f f Out = 8 / has to be evenly distributed across N = 3 stages: f 3 8 / has to be evenly distributed across N = 4 stages: f 4 8? Digital I 53
Otimum Number of Stages For a given load, and given inut caacitance in Find otimal sizing f t Nt ln F ln f / N F / t f 0 0 t f F t 0 ln F ln For = 0, f = e, N = lnf in f N f in with ln f N f f ln ln 0 F f e f Digital I 54
Otimum Effective Fanout f Otimum f for given rocess defined by f e f f ot = 3.6[4] for = Digital I 55
Imact of Self-oading on t No Self-oading, =0 With Self-oading = 7 60.0 6 5 u/ln(u) 40.0 x=0,000 x=000 4 3 0.0 x=00 x=0 0.0.0 3.0 5.0 7.0 u 0.5.5 3 3.5 4 4.5 5 Digital I 56
Normalized delay function of F f = N F, N = ln F ln f = ln F ln 3.6 = 0.78ln F t = Nt 0 ( ) N + F / γ = 0.78ln F(+3.6) = 3.6ln F F unbuffered Two stages Inverter chain 0 8.3 8.3 00 0 6.6 000 00 65 4.9 0000 000 0 33 Digital I 57
Buffer Design N f t 64 64 65 8 64 8 8 4 6 64 3 4 5.8 8.6 64 4.8 5.3 Digital I 58
More general examle t = Nt0 ( ) + f / γ 4 F = f = 4 = 3 4 = 6 3 = 3 3 = f 3 = 6 4 4 in 3 3 out 3 = 6 3 f 3 = f = 4 64 3 6 = 4 3 4 = 4 f 3 = 4*4 4 3 3 6 4 = 3 6 Digital I Slide 59
Design hallenge A gate is never designed in isolation: its erformance is affected by both the fan-out and the driving strength of the gate(s) feeding its inuts. t i = t Digital I ( 0.5) Kee signal rise times smaller than or equal to the gate roagation delays good for erformance good for ower consumtion i ste + ηt Keeing rise and fall times of the signals small and of arox. equal values is one of the major challenges in high-erformance designs(sloe engineering.) i- ste
Inut Signal Rise/Fall Time In reality, the inut signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging and imacts roagation delay. t increases linearly with increasing inut sloe, t s, once t s > t t s is due to the limited driving caability of the receding gate 5.4 5. 5 4.8 4.6 4.4 4. 4 3.8 x 0 - t s (sec) 3.6 0 4 6 8 for a minimum-size inverter with a fanout of a single gate x 0 - Digital I
Rising-fall time of the inut signal t i = t i ste + ηt i- ste Note: t increases linearly with increasing inut sloe,once t s >t (t s =0) in out 3 Digital I Slide 6