COE 202: Digital Logic Design Sequential Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324
Objectives State Reduction and Assignment Design of Synchronous Sequential Circuits Procedure Examples
State Reduction The process of reducing the number of states It results in less Flip flops It may increase the combinational logic!
State Reduction (Example) Is it possible to reduce this FSM? Notes: we use letters to denote states rather than binary codes we only consider input/output sequence and transitions
State Reduction (Example) Step 1: get the state table
State Reduction (Example) Step 1: get the state table Step 2: find similar states e and g are equivalent states remove g and replace it with e
State Reduction (Example) Step 1: get the state table Step 2: find similar states e and g are equivalent states remove g and replace it with e
State Reduction (Example) Step 1: get the state table Step 2: find similar states d and f are equivalent states remove f and replace it with d
State Reduction (Example) Step 1: get the state table Step 2: find similar states d and f are equivalent states remove f and replace it with d
State Reduction (Example) Reduced FSM Verify sequence: State a a b c d e f f g f input 0 1 0 1 0 1 1 0 1 output 0 0 0 0 0 1 1 0 1
State Assignmnet State Assignment: Assign unique binary codes to the states Example Three Possible Assignments:
Design of Synchronous Sequential Circuits Obtain a state diagram State reduction if necessary Obtain State Table State Assignment Choose type of flip-flops Use FF s excitation table to complete the table Derive state equations Use K-Maps Obtain the FF input equations and the output equations Draw the circuit diagram
Example 1 Problem: Design of A Sequence Recognizer Design a circuit that reads as inputs continuous bits, and generates an output of 1 if the sequence (1011) is detected X Y Input 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 Output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0
Example 1 (cont.) Step1: State Diagram Sequence to be detected:1011
Example 1 (cont.) Step 2: State Table OR
Example 1 (cont.) Step 2: State Table state assignment Q: How many FF? log 2 (no. of states)
Example 1 (cont.) Step 2: State Table choose FF In this example, lets use JK FF for A and D-FF for B
Example 1 (cont.) Step 2: State Table complete state table use excitation tables for JK FF and D-FF Next State output D FF excitation table JK FF excitation table
Example 1 (cont.) Step 3: State Equations use k-map J A = BX K A = BX + B X D B = X Y = ABX
Example 1 (cont.) Step 4: Draw Circuit J A = BX K A = BX + B X D B = X Y = ABX
Example 2 Problem: Design of A 3-bit Counter Design a circuit that counts in binary form as follows 000, 001, 010, 111, 000, 001,
Example 2 (cont.) Step1: State Diagram - The outputs = the states - Where is the input? - What is the type of this sequential circuit?
Example 2 (cont.) Step2: State Table No need for state assignment here
Example 2 (cont.) Step2: State Table T FF excitation table We choose T-FF
Example 2 (cont.) Step3: State Equations
Example 2 (cont.) Step4: Draw Circuit T A0 = 1 T A1 = A 0 T A2 = A 1 A 0
Example 3 Problem: Design of A Sequence Recognizer Design a Moore machine to detect the sequence (111). The circuit has one input (X) and one output (Z).
Example 3 (cont.) Step1: State Diagram Sequence to be detected:111 0 1 1 0 1 S0/0 S1/0 S2/0 S3/1 1 0 0
Example 3 (cont.) Step2: State Table Use binary encoding Use JK-FF and D-FF 0 1 1 0 S0/0 S1/0 S2/0 1 S3/1 1 0 0
Example 3 (cont.) Step4: Draw Circuit For step3, use k-maps as usual J A = XB K A = X D B = X(A+B) Z = A.B
Example 3 (cont.) Timing Diagram (verification) Question: Does it detect 111?
Example 4 Problem: Design a traffic light controller for a 2-way intersection. In each way, there is a sensor and a light N Traffic Action EW only EW Signal green NS Signal red W E NS only NS Signal green EW Signal red EW & NS Alternate No traffic Previous state S
Example 4 (cont.) Step1: State Diagram 11, 10 00, 01 00, 10 NS / 01 EW / 10 11, 01 STATES NS: NS is green EW: EW is green INPUTS Sensors X 1, X 0 X 0 : car coming on NS X 1 : car coming on EW OUTPUTS Light S 1, S 0 S 0 : NS is green S 1 : EW is green
Example 4 (cont.) Exercise: Complete the design using: D-FF JK-FF T-FF
Example 5 Problem: Design Up/Down counter with Enable Design a sequential circuit with two JK flip-flops A and B and two inputs X and E. If E = 0, the circuit remains in the same state, regardless of the input X. When E = 1 and X = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11, back to 00, and then repeats. When E = 1 and X = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01, back to 00 and then repeats.
Example 5 (cont.) Present State Inputs Next State FF Inputs 00 01 00 01 00 01 11 10 11 11 10 11 10 11 10 10 00 01 00 01 A B E X A B J A K A J B K B 0 0 0 0 0 0 0 X 0 X 0 0 0 1 0 0 0 X 0 X 0 0 1 0 1 1 1 X 1 X 0 0 1 1 0 1 0 X 1 X 0 1 0 0 0 1 0 X X 0 0 1 0 1 0 1 0 X X 0 0 1 1 0 0 0 0 X X 1 0 1 1 1 1 0 1 X X 1 1 0 0 0 1 0 X 0 0 X 1 0 0 1 1 0 X 0 0 X 1 0 1 0 0 1 X 1 1 X 1 0 1 1 1 1 X 0 1 X 1 1 0 0 1 1 X 0 X 0 1 1 0 1 1 1 X 0 X 0 1 1 1 0 1 0 X 0 X 1 1 1 1 1 0 0 X 1 X 1
Example 5 (cont.) EX AB 00 01 11 10 EX AB 00 01 11 10 E X 00 0 0 0 1 01 0 0 1 0 00 x x x x 01 x x x x Y 11 x x x x 10 x x x x 11 0 0 1 0 10 0 0 0 1 J A C A J A = BEX + B EX K A = BEX + B EX K A A EX AB 00 01 11 10 EX AB 00 01 11 10 B 00 0 0 1 1 01 x x x x 00 x x x x 01 0 0 1 1 J B C K B B 11 x x x x 10 0 0 1 1 J B = E 11 0 0 1 1 10 x x x X K B = E clock
More Examples More design examples can be found at Homework 5 Textbook Course CD Google
Summary To design a synchronous sequential circuit: Obtain a state diagram State reduction if necessary Obtain State Table State Assignment Choose type of flip-flops Use FF s excitation table to complete the table Derive state equations Use K-Maps Obtain the FF input equations and the output equations Draw the circuit diagram