FEATURES Provides arithmetic operation: add, subtract, compare, and double; plus 12 other arithmetic operatio Provides all logic operatio of two variables: Exclusive-OR, Compare, AND, NAND, NOR, OR, plus 10 other logic operatio Full look-ahead carry for high speed arithmetic operation on long words 0% faster than S181 with only 0% S181 power coumption Available in 00mil-wide Slim 2-pin Dual In-Line package DESCRIPTION The is a -bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0 S) and the Mode Control input (M), it can perform all the possible logic operatio or different arithmetic operatio on active-high or active-low operands. The Function Table lists these operatio. PIN CONFIGURATION B0 1 2 A0 S S2 S1 S0 Cn M F0 F1 F2 GND 2 5 6 8 9 10 11 12 2 22 21 20 19 18 1 1 1 V CC A1 B1 A2 B2 A B G C n+ P A=B F SF0019 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) ma ORDERING INFORMATION DESCRIPTION 2-Pin Plastic Slim DIP (00 mil) 2-Pin Plastic SOL COMMERCIAL RANGE V CC = 5V ±10%, T amb = 0 C to +0 C NN ND INPUT AND OUTPUT LOADING AND FAN-OUT TABLE NOTE: PINS DESCRIPTION F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 A A operand inputs 1.0/ 20µA/1.8mA B0 B B operand inputs 1.0/ 20µA/1.8mA M Mode control input 1.0/1.0 20µA/0.6mA S0 S Function select input 1.0/ 20µA/2.mA Cn Carry input 1.0/ 20µA/mA C n+ Carry output 50/ 1.0mA/20mA P Carry Propagate output 50/ 1.0mA/20mA G Carry Generate output 50/ 1.0mA/20mA A=B Compare output OC/ OC/20mA F0 F Outputs 50/ 1.0mA/20mA One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. OC = Open Collector March, 1989 1 85 051 959
LOGIC SYMBOL IEC/IEEE SYMBOL 8 6 5 Active-High Operands 2 1 2 22 21 20 19 18 A0 B0 A1 B1 A2 B2 A B Cn M S0 S1 S2 C n+ A=B G P S F0 F1 F2 F 9 10 11 1 1 1 6 ALU 0 [T] 5 M 0 CP 21 CG CO 8 P=G CI 2 1 P0 Q0 2 P1 22 Q1 21 P2 20 Q2 19 P 18 Q 1 1 9 10 11 1 Active-Low Operands SF0019 2 1 2 22 21 20 19 18 8 6 5 A0 B0 A1 B1 A2 B2 A B Cn M S0 S1 S2 C n+ A=B G P S F0 F1 F2 F 1 1 V CC = Pin 2 GND = Pin 12 9 10 11 1 SF00196 March, 1989 2
LOGIC DIAGRAM S0 6 S1 5 S2 S B 18 1 G A 19 C n+ B2 20 P A2 21 B1 22 1 F A1 2 11 F2 B0 1 1 A=B A0 2 M 8 Cn 10 9 F1 F0 V CC = Pin 2 GND = Pin 12 SF0019 March, 1989
When the Mode Control input (M) is High, all internal carries are inhibited and the device performs logic operatio on the individual bits as listed. When the Mode control input is Low, the carries are enabled and the device performs arithmetic operatio on the two -bit words. The device incorporates full internal carry look-ahead and provides for either ripple carry between device using the C n+ output, or for carry look-ahead between packages using the signals P (Carry Propagate) and G (Carry Generate). P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (C n+ ) signal to the Carry input (Cn) of the next unit. For high-speed operation, the device is used in conjunction with the F182 carry look-ahead circuit. One carry look-ahead package is required for each group of four devices. Carry look-ahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A=B output from the device goes High when all four F outputs are High and can be used to indicate logic equivalence over -bits when the unit is in the subtract mode. The A=B output is open-collector and can be wired-and with other A=B outputs to give a comparison for more than bits. The A=B signal can also be used with the C n+ signal to indicate A>B and A<B. The Function Table lists the arithmetic operatio that are performed without a carry in. An incoming carry adds a one to each operation. Thus select code LHHL generates A minus B minus 1 (two s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (one s complement), a carry out mea borrow; thus, a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active-low inputs producing active-low outputs or with active-high inputs producing active-high outputs. For either case, the table lists the operatio that are performed to the operands labeled iide the logic symbol. MODE-SELECT FUNCTION TABLE MODE SELECT INPUTS ACTIVE HIGH INPUTS & OUTPUTS ACTIVE LOW INPUTS & OUTPUTS S S2 S1 S0 Logic (M=H) Arithmetic** (M=L) (Cn=H) Logic (M=H) Arithmetic** (M=L) (Cn=L) L L L L A A A A minus 1 L L L H A+B A+B AB AB minus 1 L L H L AB A+B A+B AB minus 1 L L H H Logical 0 minus 1 Logical 1 minus 1 L H L L AB A plus AB A+B A plus (A+B) L H L H B (A+B) plus AB B AB plus (A+B) L H H L A B A minus B minus 1 A B A minus B minus 1 L H H H AB AB minus 1 A+B A+B H L L L A+B A plus AB AB A plus (A+B) H L L H A B A plus B A B A plus B H L H L B (A+B) plus AB B AB plus (A+B) H L H H AB AB minus 1 A+B A+B H H L L Logical 1 A plus A* Logical 0 A plus A* H H L H A+B (A+B) plus A AB AB plus A H H H L A+B (A+B) plus A AB AB plus A H H H H A A minus 1 A A H = High voltage level L = Low voltage level * = Each bit is shifted to the next more significant position. ** = Arithmetic operatio expressed in two s complement notation. March, 1989
Table 1. Sum Mode Test Function Inputs: S0 = S = V, S1 = S2 = M = 0V INPUT OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER TEST Apply V Apply GND Apply V Apply GND UNDER TEST, A i B i None Remaining A and B Cn F i, B i A i None Remaining A and B Cn F i, A i B i None None Remaining A, B, Cn P, B i A i None None Remaining A, B, Cn P, A i None B i Remaining B Remaining A, Cn G, B i None A i Remaining B Remaining A, Cn G, A i None B i Remaining B Remaining A, Cn C n+, B i None A i Remaining B Remaining A, Cn C n+, Cn None None All A All B Any F or C n+ Table 2. Diff Mode Test Function Inputs: S1 = S2 = V, S0 = S = M = 0V INPUT OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER TEST Apply V Apply GND Apply V Apply GND UNDER TEST, A i None B i Remaining A Remaining B, Cn F i, B i A i None Remaining A Remaining B, Cn F i, A i None B i None Remaining A, B, Cn P, B i A i None None Remaining A, B, Cn P, A i B i None None Remaining A, B, Cn G, B i None A i None Remaining A, B, Cn G, A i None B i Remaining A Remaining B, Cn A=B, B i A i None Remaining A Remaining B, Cn A=B, A i B i None None Remaining A, B, Cn C n+, B i None A i None Remaining A, B, Cn C n+, Cn None None All A and B None Any F or C n+ Table. Logic Mode Test Function Inputs: S1 = S2 = V, S0 = S = 0V INPUT OTHER INPUT, SAME BIT OTHER DATA INPUTS OUTPUT UNDER TEST Apply V Apply GND Apply V Apply GND UNDER TEST, A i B i None None Remaining A, B, Cn F i, B i A i None None Remaining A, B, Cn F i ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL RATING UNIT V CC Supply voltage 0.5 to + V V IN Input voltage 0.5 to + V I IN Input current 0 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 0 ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range 65 to +0 C March, 1989 5
RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL MIN NOM MAX UNIT V CC Supply voltage V V IH High-level input voltage 2.0 V V IL Low-level input voltage 0.8 V I IK Input clamp current 18 ma V OH High level output voltage A=B only V I OH High-level output current Any output except A=B 1 ma I OL Low-level output current 20 ma T amb Operating free-air temperature range 0 +0 C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL TEST CONDITIONS 1 MIN TYP 2 MAX UNIT I OH V OH High-level output current High-level output voltage A=B only V CC = MIN, V IL = MAX; V IH = MIN, V OH = MAX 250 µa Any output except A=B V CC = MIN, V IL = MAX, I OH = MAX V IH = MIN V CC = MIN, V OL Low-level output voltage V IL = MAX, I OL = MAX V IH = MIN ±10%V CC ±5%V CC 2.. ±10%V CC 0.0 0.50 ±5%V CC 0.0 0.50 V IK Input clamp voltage V CC = MIN, I I = I IK 0. 1.2 V I I Input current at maximum input voltage V CC = MAX, V I = V 100 µa I IH High-level input current V CC = MAX, V I = 2.V 20 µa I IL I OS I CC Low-level input current Short-circuit output current Supply current (total) M 0.6 ma A0 A, B0 B S0 S V CC = MAX, V I = 0.5V V V 1.8 ma 2. ma Cn ma Any output except A=B I CCH V CC = MAX I CCL V CC = MAX 60 0 ma S0 S=M=A0 A=V, B0 B=Cn=GND S0 S=M=V, B0 B=Cn=A0 A=GND 65 ma 65 ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C.. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. March, 1989 6
AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL TEST CONDITIONS V CC = +V T amb = +25 C C L = 50pF R L = 500Ω V CC = +V ± 10% T amb = 0 C to +0 C C L = 50pF R L = 500Ω UNIT Mode Table Waveform Condition MIN TYP MAX MIN MAX Cn to C n+ Sum Diff 1 2 1 M=0V Sum 1 2 M=S1=S2=0V, An or Bn to C n+ S0=S=V 12.0 12.0 1 1 Diff 2 2 M=S0=S=0V, An or Bn to C n+ S1=S2=V 1 12.0 1 1 Cn to Fn Diff Sum 2 1 1 M=0V An or Bn to G Sum 1 1 M=S1=S2=0V, S0=S=V An or Bn to G Diff 2 2 M=S0=S=0V, S1=S2=V An or Bn to P Sum 1 2 M=S1=S2=0V, S0=S=V 2.0 An or Bn to P Diff 2 1, 2 M=S0=S=0V, S1=S2=V 2.0 Sum 1 1, 2 M=S1=S2=0V, A i or B i to F i S0=S=V Diff 2 1, 2 M=S0=S=0V, A i or B i to F i S1=S2=V An or Bn to Fn Sum 1, 2 An or Bn to Fn Diff 1, 2 6.5 Logic 1, 2 M=V A i or B i to F i An or Bn to A=B Diff 2 1, 2 M=S0=S=0V, S1=S2=V NOTES: An or Bn to Fn mea any A or any B to any F; A i or B i to F i mea A1, B1 to F1; A2, B2 to F2 (the identifying number must be the same). 1 1 1 20.5 1 March, 1989
AC ELECTRICAL CHARACTERISTICS SYMBOL S i to F i (Inverting) S i to F i (Non-Inverting) S i to A=B (Inverting) S i to A=B (Non-Inverting) S i to C n+ (Inverting) S i to G (Non-Inverting) S i to P (Non-Inverting) M to F i (Inverting) M to F i (Non-Inverting) M to F i (Inverting) M to F i (Non-Inverting) M to A=B (Inverting) M to A=B (Non-Inverting) M to A=B (Inverting) M to A=B (Non-Inverting) TEST CONDITIONS V CC = +V T amb = +25 C C L = 50pF R L = 500Ω LIMITS V CC = +V ± 10% T amb = 0 C to +0 C C L = 50pF R L = 500Ω Mode Waveform MIN TYP MAX MIN MAX 1 2 1 2 1 2 2 Sum 1 Sum 2 Diff 1 Diff 2 Sum 1 12.0 6.5 Sum 2 1 6.5 Diff 1 11.5 Diff 2 1.5 1 1 1 1 1 2 1 1 6.5 20.0 21.0 20.0 21.5 12.0 1 2 11.5 21.0 1 1 11.5 22.0 2 11.5 22.0 2 11.5 UNIT AC WAVEFORMS For all waveforms, = 1.5V. V IN V IN V OUT V OUT SF00092 SF0009 Waveform 1. Propagation Delay for Non-Inverting Paths Waveform 2. Propagation Delay for Inverting Paths March, 1989 8
TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR V IN V CC D.U.T. V OUT R L V NEGATIVE PULSE 90% 10% t THL ( t f ) t w t TLH ( t r ) 10% 90% AMP (V) 0V R T C L R L Test Circuit for Open Collector Outputs SWITCH POSITION TEST SWITCH Open Collector closed All other open POSITIVE PULSE 10% t TLH ( t r ) t THL ( t f ) 90% 90% t w Input Pulse Definition 10% AMP (V) 0V DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family F INPUT PULSE REQUIREMENTS amplitude rep. rate t w t TLH t THL V 1.5V 1MHz 500 SF00195 March, 1989 9