THE INVERTER
DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy
Noise in Digital Integrated Circuits v(t) V DD i(t) (a) Inductive coupling (b) Capacitive coupling (c) Power and ground noise
DC Operation: Voltage Transfer Characteristic V(y) V(x) V(y) V OH f V(y)=V(x) V M Switching Threshold V OL V OL V OH V(x) Nominal Voltage Levels
Mapping between analog and digital signals "1" V OH V IH V(y) V OH Slope = -1 Undefined Region Slope = -1 V IL "0" V OL V OL V V IL IH In real life applications, output voltage of a gate may not have the nominal value Owing to load, high switching speed, etc. Hence, it is desirable to define an acceptable voltage range for logic 1 and logic 0, respectively V(x)
Definition of Noise Margins "1" V OH Noise Margin High Noise Margin Low V OL "0" Gate Output NM H NM L V IH Undefined Region V IL Gate Input
The Regenerative Property v 0 v 1 v 2 v 3 v 4 v 5 v 6... (a) A chain of inverters. v 1, v 3,... v 1, v 3,... f(v) finv(v) finv(v) f(v) v 0, v 2,... (b) Regenerative gate v 0, v 2,... (c) Non-regenerative gate
Fan-in and Fan-out (a) Fan-out N M N (b) Fan-in M
The Ideal Gate V out R i = g= R o = 0 V in
VTC of Real 5.0 4.0 NM L V out (V) 3.0 2.0 V M 1.0 NM H 0.0 1.0 2.0 3.0 4.0 5.0 V in (V)
Delay Definitions V in 50% t phl t plh t V out 90% 50% t f 10% t r t
Ring Oscillator v 0 v 1 v 2 v 3 v 4 v 5 v 0 v 1 v 5 T = 2 t p N
Power Dissipation
CMOS INVERTER
The CMOS : A First Glance V DD V in V out C L
CMOS s PMOS V DD In Out 1.2 µm =2λ Metal1 Polysilicon NMOS GND
Switch Model of CMOS Transistor V GS R on V GS < V T V GS > V T
CMOS : Steady State Response V DD V DD R on V OH = V DD V out V out V OL = 0 R on V M = f(r onn, R onp ) V in = V DD V in = 0
CMOS : Transient Response V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD 0.5 0.36 V in = V DD R on C L t
CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching
Voltage Transfer Characteristic
PMOS Load Lines V in = V DD -V GSp I Dn = - I Dp I Dn V out = V DD -V DSp V out I Dp V in =0 I Dn I Dn V in =0 V in =3 V in =3 V GSp =-2 V DSp V DSp V out V GSp =-5 V in = V DD -V GSp I Dn = - I Dp V out = V DD -V DSp
CMOS Load Characteristics I n,p V V = 5 in = 0 in PMOS NMOS V in = 4 V in = 1 V in = 4 V in = 3 V in = 2 V in = 3 V in = 2 V in = 4 V in = 5 V in = 3 V in = 2 V in = 1 V in = 0
CMOS VTC V out NMOS off PMOS lin 1 2 3 4 5 NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat NMOS lin PMOS off 1 2 3 4 5 V in
Simulated VTC 4.0 V out (V) 2.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 V in (V)
Gate Switching Threshold 4.0 3.0 V M 2.0 1.0 0.1 0.3 1.0 3.2 10.0 k p /k n
MOS Transistor Small Signal Model G v gs + g m v gs r o D - S
Determining V IH and V IL
Propagation Delay
CMOS : Transient Response V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD 0.5 0.36 V in = V DD R on C L t
CMOS Propagation Delay V DD t phl = C L V swing /2 I av I av V out C L ~ C L k n V DD V in = V DD
Computing the Capacitances V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L
CMOS s PMOS V DD In Out 1.2 µm =2λ Metal1 Polysilicon NMOS GND
The Miller Effect V C gd1 V out V out V V in V 2C gd1 M1 V V in M1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.
Computing the Capacitances
Impact of Rise Time on Delay 0.35 0.3 t phl (nsec) 0.25 0.2 0.15 0 0.2 0.4 0.6 t rise (nsec) 0.8 1
Delay as a function of V DD 28 24 Normalized Delay 20 16 12 8 4 0 1.00 2.00 3.00 4.00 5.00 V DD (V)
Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors
Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power.
Impact of Technology Scaling
Technology Evolution
Technology Scaling (1) Minimum Feature Size
Technology Scaling (2) Number of components per chip
Propagation Delay Scaling
Technology Scaling Models Full Scaling (Constant Electrical Field) ideal model dimensions and voltage scale together by the same factor S Fixed Voltage Scaling most common model until recently only dimensions scale, voltages remain constant General Scaling most realistic for todays situation voltages and dimensions scale with different factors
Scaling Relationships for Long Channel Devices
Scaling of Short Channel Devices