V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH RXLK ETH TX[0:] ETH TXEN ETH TXER ETH TXLK ETH RS ETH OL_ ETH MIO ETH M ETH SPEE ETH RX[0:] ETH RXV ETH RXER ETH RXLK ETH TX[0:] ETH TXEN ETH TXER ETH TXLK ETH RS ETH OL_ ETH MIO ETH M ETH SPEE TWI_T TWI_LK GPIO[0:] EIM_EXTINT_[:] PM_WKE_N V. ETH RX[0:] ETH TX[0:] SPI_SK SPI_NPS[0:] SS R SS RF SS RK SS T SS TF SS TK SS R SS RF SS RK SS T SS TF SS TK SPI_NPS[0:] V. SPI_SK SPI_NPS[0:] PM_WKE_N SS R SS RF SS RK SS T SS TF SS TK SS R SS RF SS RK SS T SS TF SS TK EIM_EXTINT_[:] connectors _TS_EXPHR _RX_EXPHR _RX_EXPHR N[0:] [0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] GPIO[0:] TWI_LK TWI_T URT LK URT RTS URT TX URT TX TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] GPIO[0:] V. V. V. V. TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] GPIO[0:] TWI_LK TWI_T URT LK URT TS URT RTS URT TX URT RX URT LK URT TS URT RTS URT TX URT RX URT LK URT TS URT RTS URT TX URT RX MK M[0:] M PS T PS LOK PS T M[0:] M PS LOK URT LK URT TS URT RTS URT TX URT RX ETH RX[0:] ETH RXV ETH RXER ETH RXLK ETH TX[0:] ETH TXEN ETH TXER ETH TXLK ETH RS ETH OL_ ETH MIO aughterboard connector PWM[:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] ETH M ETH SPEE TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] ETH SPEE ETH M ETH MIO ETH OL_ ETH RS ETH TXLK ETH TXER ETH TXEN ETH TX[0:] ETH RXLK ETH RXER ETH RXV ETH RX[0:] US_M US_P US_VUS US_I N[0:] [0:] _SLK _SYN _SI _SO PM_GLK_[:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] ETH TX[0:] ETH RX[0:] US_M US_P US_VUS US_I _SLK _SYN _SI _SO PM_GLK_[:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] [0:] [0:] N[0:] PWM[:] P MK M[0:] M TMEL S Vestre Rosten N-0 TILLER TSTK000 - Top level 00..000. Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
PM_GLK_[:] [0:] SS TK SS TF SS T SS RK SS RF SS R SS TK SS TF SS T SS RK SS RF SS R SPI_SK SPI_NPS[0:] udio SS TK SS TF PM_GLK_[:] SS T /SPI_OUT /SPI_IN SPI_SK SPI_NPS0/_S SPI_NPS0 SPI_NPS[0:] PM_GLK_ PM_GLK_/_MLK [0:] [0:] HSL HSR SPI_SK SPI_NPS[0:] V. V. V. V. SS TK SS TF SS T SS RK SS RF SS R SS TK SS TF SS T SS RK SS RF SS R SPI_SK SPI_NPS[0:] SPI_NPS L KLIGHT_THOE V_L -0V_L V_L L_VOM L_M SPI_SK SPI_NPS L_PWR L_[0:] L_[0:] aughterboard connector EIM_EXTINT_[:] L_ L_PWR L_MOE L_VL L_PLK PM_WKE_N L_VSYN L_HSYN L_VL L_PLK L_VSYN L_HSYN L_[0:] HISI_MLK HISI_PLK HISI_VSYN US_P US_M HISI_T[0:] HISI_HSYN HISI_T[0:] US_P US_M MRQ_[:] MRQ_[:] RT_WTEXT L_ L_PWR L_MOE L_VL L_PLK L_VSYN L_HSYN L_[0:] L_M L_VOM V_L HISI_MLK HISI_PLK HISI_VSYN HISI_HSYN HISI_T[0:] HSL HSR EI_[0:] EI_S0 EI_0 EI_ EI_[0:] EI_NWR0 EI_NWR EI_NWR EI_NR EI_NS[0:] EI_NWIT EI_SKE EI_SK EI_SWE EI_RS EI_S EI_FE[:] EI_NNWE EI_NNOE EI_FRNW EI_SS RT_WTEXT MRQ_[:] -0V_L V_L L_KLIGHT_THOE SPI_SK SPI_NPS[0:] PI TWI_LK TWI_T PWM[:] URT LK URT TX EI_SS EI_FRNW EI_NNOE EI_NNWE EI_FE[:] EI_S EI_RS EI_SWE EI_SK EI_SKE EI_NWIT EI_NS[0:] EI_NR EI_NWR EI_NWR EI_NWR0 EI_[0:] EI_ EI_0 EI_S0 EI_[0:] V. V. V. V. EI_[0:] PM_GLK_[:] [0:] PI_RX EIM_EXTINT_[:] PM_WKE_N TIMER TLK0 TIMER TIO0 TIMER TIO0 _SLK _SYN _SO _SI EI_[0:] EI_[0:] EI_NS[0:] EI_FE[:] EI_[0:] EI_S0 Memories EI_0 EI_ EI_[0:] EI_NWR0 EI_NWR EI_NWR EI_NR EI_NS[0:] EI_NWIT EI_SKE EI_SK EI_SWE EI_RS EI_S EI_FE[:] Power MK M[0:] M V. V. GPIO GPIO GPIO GPIO0 GPIO V. V. TIMER TLK0 TIMER TIO0 TIMER TIO0 EIM_EXTINT_E/FREY GPIO/FVS GPIO/FINPK GPIO/F GPIO0/S GPIO/SWP EIM_EXTINT_ V. V. TWI_LK TWI_T PWM[:] URT LK URT TX PI_RX TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] _SLK _SYN _SO _SI MK M[0:] M GPIO[0:] GPIO[0:] Leds nd Switches EIM_EXTINT_[:] EIM_EXTINT_[:] US_P US_M US_P US_M US EIM_EXTINT_[:] US_VUS US_M US_P US_I US_VUS US_M US_P US_I PM_WKE_N EIM_EXTINT_[:] PM_WKE_N TMEL S Vestre Rosten N-0 TILLER Size TSTK000 - Top level ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
V. V. 00 0 0 0 V. V. J MIT-0-0-F--K 0 0 0 0 0 0 0 center connectors EI_0 EI_0 EI_[0:] EI_[0:] EI_NS[0:] EI_FE[:] EI_SS EI_NWR0 EI_NWR EI_RS EI_SWE EI_NWIT EI_NNWE L_HSYN L_VSYN L_MOE L_[0:] HISI_T[0:] HISI_HSYN HISI_PLK MRQ_[:] RT_WTEXT SS RF SS TK SS T SS RF SS TK SS T SPI_SK US_M US_M EI_NS0 EI_SS EI_NWR0 EI_NWR EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_RS EI_SWE EI_ EI_NS EI_NS V. V. EI_0 EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_0 EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_FE EI_FS EI_NWIT EI_NNS EI_NNWE L_HSYN L_VSYN L_MOE L_0 L_ L_ L_ L_ L_0 L_ L_ L_ L_ L_0 L_ HISI_T0 HISI_T HISI_T HISI_T HISI_T HISI_T0 0 0 0 0 0 HISI_HSYN HISI_PLK EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ MRQ_ MRQ_ RT_WTEXT SS RF SS TK SS T SS RF SS TK SS T SPI_SK SPI_NPS US_M US_M EI_0 J 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 V. V. EI_SS0 EI_NS EI_NR EI_NWR EI_SK EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_SKE EI_S EI_S0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_FE EI_FS0 EI_NS EI_FRNW EI_NS EI_NNOE L_ L_PLK L_VL L_PWR L_ L_ L_ L_ L_ L_ L_ L_ L_ L_ L_ L_ HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T HISI_VSYN HISI_MLK EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ PM_WKE_N MRQ_ MRQ_ SS TF SS RK SS R SS TF SS RK SS R SPI_NPS0 SPI_NPS US_P US_P EI_ EI_NR EI_NWR EI_SK EI_SKE EI_S EI_S0 EI_FRNW EI_NNOE L_ L_PLK L_VL L_PWR HISI_VSYN HISI_MLK EIM_EXTINT_[:] PM_WKE_N SS TF SS RK SS R SS TF SS RK SS R SPI_NPS[0:] US_P US_P EI_ EI_ MIT-0-0-F--K TMEL S Vestre Rosten N-0 TILLER TSTK000 - aughterboard connector Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
GPIO0 GPIO GPIO GPIO GPIO GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO0 GPIO0 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO[0:] ETH OL_ ETH TXER ETH TX ETH TX ETH TXLK ETH RX ETH RX ETH RXLK ETH M ETH SPEE ETH RS ETH TX0 ETH RS ETH TX0 ETH TX ETH TXEN ETH RX0 ETH RX ETH RXER ETH RXV ETH MIO ETH OL_ ETH TXER ETH TX ETH TX[0:] ETH RX[0:] ETH TX ETH TXEN ETH RX0 ETH RXER ETH RX ETH RXV ETH MIO ETH RX ETH TXLK ETH TX ETH M ETH SPEE ETH RX ETH RXLK ETH TX[0:] ETH RX[0:] TWI_T URT RTS URT RX URT LK URT TS URT TX URT RTS TWI_LK URT TS URT TX URT RTS URT RX URT LK URT TS URT RX URT LK URT TS URT TX URT TX URT RTS URT RX URT LK US_VUS US_M PM_GLK_ PM_GLK SLK _SO N PWM PWM TIMER TLK TIMER TIO TIMER TIO TIMER TIO0 TIMER TLK TIMER TIO TIMER TIO0 TIMER TIO TIMER TLK0 TIMER TLK TIMER TIO TIMER TIO TIMER TIO0 PS T PS T M M M M M0 MK _SYN N0 0 PWM PWM M0 M M M M TIMER TIO TIMER TIO0 PS LOK TIMER TLK0 PS LOK US_P US_I PM_GLK_ PM_GLK SI TIMER TIO TIMER TLK TIMER TIO TIMER TIO0 TIMER TLK0 TIMER TIO TIMER TLK TIMER TIO0 TIMER TIO TIMER TLK TIMER TIO V. V. GPIO[0:] ETH OL_ ETH RXLK ETH SPEE ETH M ETH TXLK ETH TXER ETH RX[0:] ETH TXEN ETH RS ETH RXER ETH RXV ETH MIO ETH TX[0:] ETH RX[0:] ETH TX[0:] ETH SPEE ETH M ETH TXLK ETH TXER ETH OL_ ETH RXLK ETH RS ETH TXEN ETH RXER ETH RXV ETH MIO TWI_T TWI_LK URT RTS URT TS URT RX URT LK URT TX URT RTS URT TS URT TX URT RX URT LK URT TS URT TX URT RX URT LK URT TX URT TS URT RTS URT LK URT RX URT RTS MK M[0:] M[0:] M M PS LOK PS LOK PS T PS T TIMER TLK[0:] TIMER TLK[0:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] PWM[:] [0:] N[0:] _SLK _SYN _SO _SI US_M US_P US_VUS US_I PM_GLK_[:] V. V. V. V. V. V. Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - aughterboard connector Tuesday, September, 00 Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - aughterboard connector Tuesday, September, 00 Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - aughterboard connector Tuesday, September, 00 Pull-up on ETH interfaces to avoid floating inputs when switch is not connecting PHY to PU on daughterboard RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP0 00k RP0 00k RP0 00k RP0 00k RP 00k RP 00k RP0 00k RP0 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP0 00k RP0 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k MIT-0-0-F--K J MIT-0-0-F--K J 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k center connectors MIT-0-0-F--K J center connectors MIT-0-0-F--K J 00 0 0 0 0 0 0 0 0 0 0 RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k RP 00k
SP S0-MN 00n [0:] 0 UXN 0n UXP R 0R L L 0n LINER 0n LINEL HSL HSR 0n JP 00 X speaker interface HSL HSL JP PIN HEER x 0 0n 0 0n uf HSR HSR R 00R uf J uf U VT P 0 0 0 uf -0 HPP HPN LPHN PINP MONOP PINN MONON LINEL LINER UXP UXN HSL HSR IN VIG V VHS VREF VM SPI_OUT SPI_IN SPI_LK SPI_S SMOE MLK 0 SIN LRFS LK RESET T package: QFN- 00n 00n 00n 0 uf R 0R R R R R R 0 0 uf U TP IN TP TP TP V TP S00LZ- SPI_SK SPI_NPS0 SS T SS TF SS TK PM_GLK_ /SPI_OUT /SPI_IN SPI_SK SPI_NPS0/_S SS T SS TF SS TK PM_GLK_/_MLK R 0R R k R k JP PIN HEER x TMEL S Vestre Rosten N-0 TILLER TSTK000 - udio Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
V. GPIO[0:] GPIO0 GPIO GPIO GPIO J 0 00 X GPIO GPIO GPIO GPIO V. GPIO GPIO0 GPIO GPIO J 0 GPIO GPIO GPIO GPIO SPI_NPS[0:] 00 X SPI_SK SS RF SS TK SS T SS RF SS TK SS T SPI_SK SPI_NPS SS RF SS TK SS T SS RF SS TK SS T EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ J 0 0 0 0-- V. SPI_NPS0 SPI_NPS SS TF SS RK SS R SS TF SS RK SS R EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ PM_WKE_N TIMER TIO SS TF SS RK SS R SS TF SS RK SS R PM_WKE_N GPIO GPIO GPIO0 GPIO GPIO GPIO GPIO GPIO0 J 0 00 X J 0 00 X GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO EIM_EXTINT_[:] TIMER TLK[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TIO[0:] TIMER TLK[0:] TWI_T URT RTS _RX_EXPHR URT LK URT TX TIMER TLK0 TIMER TIO TIMER TIO0 TIMER TIO TIMER TLK TIMER TIO0 TIMER TIO TIMER TIO TIMER TLK N TWI_T URT RTS _RX_EXPHR URT LK URT TX TP J 0 0 0 TIMER TIO0 TIMER TIO TIMER TIO TIMER TLK TIMER TLK0 TIMER TIO TIMER TIO0 TIMER TIO TIMER TLK 0 N0 TWI_LK _TS_EXPHR URT TX _RX_EXPHR TP TP TWI_LK _TS_EXPHR URT TX _RX_EXPHR 0-- R0 N[0:] J [0:] SPI_SK 00 X SPI header TMEL S Vestre Rosten N-0 TILLER TSTK000 - Pin headers Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
V. V. ETH SPEE ETH OL_ ETH RS ETH M ETH MIO ETH RXLK ETH RX[0:] ETH RXV ETH RXER ETH TXLK ETH TX[0:] ETH TXEN ETH TXER ETH RX0 ETH RX ETH RX ETH RX ETH TX0 ETH TX ETH TX ETH TX 0 U SPEE0UTO_NEG0 OL0 UPLEX0 RS0 FIER_TP0 M0 MIO0 PWRWN0 TEST0 RXLK0 MIS0 RX0_0 S0 RX0_ TXSLEW0 RX0_ RX0_ LE0_ RXV0 LE0_ RXER0 LE0_ TXLK0 TX0_0 TX0_ TX0_ TX0_ TXEN0 TXER0 SLXTQS PN_0 PP_0 PN_0 PP_0 0 0 0 0 TX0- TX0+ RX0- RX0+ R.k R.k R.k R.k LESP0 LET_LINK0 R.k J T+ T R+ T T- R- Shield Shield J00-NL nf R R R R Green Yellow 0 R 00R R0 00R LET_LINK0 LESP0 R.k R0.k R.k R.k ETH SPEE ETH OL_ ETH RS ETH M ETH MIO ETH RXLK ETH RX[0:] ETH RXV ETH RXER ETH TXLK ETH TX[0:] ETH TXEN ETH TXER R.k R.k R.k ETH RX0 ETH RX ETH RX ETH RX ETH TX0 ETH TX ETH TX ETH TX R.k R.k R.k U SPEEUTO_NEG OL UPLEX RS FIER_TP M MIO PWRWN TEST RXLK MIS RX_0 S RX_ TXSLEW RX_ RX_ LE_ RXV LE_ RXER LE_ 0 00 SLXTQS U TXLK TX_0 TX_ TX_ TX_ TXEN TXER VPEL S T 0 T R R PEL IO LE_FG IO LE_FG0 IO IO 0 R R R R VT VT RESET VR VR REFLK V V 0 SLXTQS PN_ PP_ PN_ PP_ TX- TX+ RX- RX+ V. R.k OUT LV--M0000 LESP LET_LINK V U EN J T+ T R+ T T- R- uf Shield Shield J00-NL nf uf uf R R R R uf Green Yellow 0 TMEL S Vestre Rosten N-0 TILLER R 00R R 00R LET_LINK LESP TSTK000 - Ethernet Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
R0 k 0 00n L_ONNETE R0 k KLIGHT_THOE KLIGHT_NOE R0 00 0k TS 00 uf uf uf R0 0k L_M SPI_NPS SPI_SK L_[0:] L_HSYN L_VSYN L_PLK V_L -0V_L V_L L_VOM L_[0:] KLIGHT_THOE KLIGHT_NOE L_M SPI_NPS SPI_SK L_ L_ L_ L_ L_0 L_ L_ L_ L_ L_ L_0 L_ L_ L_ L_ L_ L_0 L_ L_ L_ L_ L_ L_ L_ L_HSYN L_VSYN L_PLK V_L -0V_L V_L L_VOM 0 0 0 0 0 hold_contact hold_contact J 0000000+ uf uf uf uf TMEL S Vestre Rosten N-0 TILLER TSTK000 - L onnector Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
NOTE: Separate S and P planes are placed on the P for U R0 0R L Supply LE Indicator LE QTLP0TR UF SNT0R U SNT0R 0 0 uf.n PG_L_POWER R 0k R 00k 0n R k TP 0 00n U RY F INTG IN REF FP FN R 0k R0 R 0k k L T LX P SUPP RVP SUPN RVN 0 SHN MXEUE+ 00PS-0KL 0p uf TS TS +V uf uf uf TS uf TS TS 0 TS uf uf R 0k R k V_L 0 uf -V_L uf V_L 0 uf L_M R.k R 0k R 0k -V_L J L Supply Testpoints R0 0k U LMM L_VOM V_L V_L L_VOM L_VOM L_M L_M V_L V_L -0V_L -0V_L -0V_L uf 0 uf U VIN L 00PS-0KL SW TS KLIGHT_NOE KLIGHT_NOE L_ONNETE L_ONNETE U SNT0R SHN LMXMF F TS R k R R KLIGHT_THOE TMEL S Vestre Rosten N-0 TILLER KLIGHT_THOE KLIGHT_THOE TSTK000 - L Power Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
L VG_ LMPG0SNL L0 00n 00n 0 uf LMPG0SNL VG_ L_[0:] VG monitor should not place load directly on MU pins. V inverter used to reuse component used elsewhere in design. L_PLK VG_ U L_PWR L_VL R 0R VG_ L_0 L_ L_ L_ L_ L_ L_ L_ L_ L_ L_0 L_ L_ L_ L_ L_ L_ L_ L_ L_ L_0 L_ L_ L_ VG_ 0 0 0 SYN R0 R R R R R R R G0 G G G G G G G 0 LK PSVE LNK RSET V V V IOR IOR IOG IOG IO IO VREF OMP VKSTZ0 0 VG_ 00n VG_ 00n VG_ R0 R IOR IOG IO R R R R 0 J LHESHR 0 00n U00 SNT0R U00 SNT0R U00 SNT0R U00 SNT0R L_HSYN L_VSYN U00F SNT0R 0 U00E SNT0R TMEL S Vestre Rosten N-0 TILLER TSTK000 - L VG Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet 0 of
RP 00k RP 00k RP 00k RP 00k J 0 00 X RP 00k RP 00k RP 00k RP 00k General purpose LEs LE_IO0 LE_IO LE_IO LE_IO LE_IO LE_IO LE_IO LE_IO U U UF UE 0 U U SNT0R SNT0R SNT0R SNT0R SNT0R U SNT0R QTLP0TR LE QTLP0TR QTLP0TR LE QTLP0TR LE SNT0R U SNT0R LE0 QTLP0TR LE QTLP0TR LE LE QTLP0TR LE QTLP0TR R 0R R 0R R 0R R 0R R 0R R 0R R 0R R 0R LE -SRVGU/TR G R RP 00k RP 00k R00.k R0.k RG LEs J0 0 00 X RP 00k RP 00k RP 00k U SNT0R U SNT0R U SNT0R R0.k LE G R -SRVGU/TR R0 R0.k.k R0.k RP 00k RP 00k RP 00k UF SNT0R 0 UE SNT0R U SNT0R TMEL S Vestre Rosten N-0 TILLER Size TSTK000 - Leds ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
00n 00n 00n RP 0k RP 0k RP 0k RP 0k RP 0k TS R 00R uf R 0k SW SKHUFE00 EIM_EXTINT_[:] EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ EIM_EXTINT_ 00n R 00n 00R R0 00R R 00R R 00R R 00R Interrupt switches SW SKHUFE00 SW0 SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 RP 0k R 0k RP Reset switch RP 0k 0k RP RP 0k 0k RP RP 0k 0k 0 J 00 X General purpose switches SW_IO SW_IO SW_IO SW_IO0 SW_IO SW_IO SW_IO SW_IO 00n 0 00n 00n 00n 00n 00n 00n 00n R 00R R 00R R 00R R 00R R 00R R0 00R R 00R R 00R SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW SKHUFE00 SW0 SKHUFE00 TMEL S Vestre Rosten N-0 TILLER TSTK000 - Switches Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_[0:] EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_FE EI_FE EI_NS EI_0 EI_ EI_NS0 EI_NS EI_ EI_NR EI_NWR/FIOW EI_NWR/FIOR M0 M M M EI_ EI_[0:] EI_[0:] GPIO/F EI_FE[:] EI_0 EI_ EI_S EI_RS EI_NS[0:] EI_SK EI_SKE EI_SWE EI_NWR EI_NWR EI_S0 EI_NWR0 EI_NR EI_NWR0 EI_NWIT GPIO/FVS EIM_EXTINT_E/FREY GPIO/FINPK GPIO/SWP GPIO0/S M[0:] M MK Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - Memories Monday, September, 00 Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - Memories Monday, September, 00 Size ocument Number Rev ate: Sheet of TMEL S Vestre Rosten N-0 TILLER T0 TSTK000 - Memories Monday, September, 00 M SRM M FLSH Footprint for M MTLM, use M MTLM J S000 J S000 0 LK M ETET 0 WP SW_OM V VSS VSS VSS N U TV-0TU U TV-0TU 0 0 E OE I/O0 I/O 0 I/O I/O I/O I/O0 I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O I/O 0 WE RESET 0 0 WP VPP VQ V R k R k R k R k R k R k R0 k R0 k R00 k R00 k J0 SF000 J0 SF000 E 0 OE 0 V 0 0 0 WP 0 E VS IOR IOWR WE REY V SEL VS 0 RESET WIT INPK REG V V 0 0 U MTLMP-:G U MTLMP-:G 0 0 0 0 0 0 0 0 0 0 0 QM0 QM QM QM WE S RS S 0 KE LK V V V V V V V V V V0 V V 0 0 N R k R k R0 k R0 k R k R k R0 k R0 k R k R k R0 k R0 k R k R k R0 k R0 k R k R k R k R k R k R k
EIM_EXTINT_ PM_GLK_[:] EIM_EXTINT_[:] MRQ_[:] HISI_T[0:] SPI_NPS[0:] PM_GLK_ PWM[:] L_[0:] V. ate: Monday, September, 00 Sheet of EI_0 EI_ EI_ EI_ EI_ EI_FE EI_FE EI_ EI_ EI_ EI_ EI_ EI_ PM_GLK EI_0 TIMER TIO0 TIMER TLK0 EI SO _SLK EI SI _SYN EIM_EXTINT_ EI_ SPI_SK PI_RX URT TX EI_NS EI_ EI_NS EI_0 EI_NS0 EI_ EI_ EI_NWR EI_ EI_ EI_ EI_NWR EI_ EI_ EI_NS0 EI_NR EI_NWR EI_NS EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ HSR -0V_L V_L V_L L_KLIGHT_THOE L_M L_VOM 0 EI_SK EI_SKE HSL EI_NS EI_NS PWM L_ PWM L_HSYN L_PLK PWM L_VSYN L_VL L_MOE L_PWR PM_GLK_ L_0 PM_GLK_ L_ L_ L_ L_ L_ L_ L_ L_ L_ L_0 PM_GLK_ L_ EIM_EXTINT_ L_ EIM_EXTINT_ L_ URT LK L_ L_ PM_WKE_N L_ L_ MRQ_ L_ L_ L_0 MRQ_ MRQ_ L_ MRQ_ L_ L_ HISI_HSYN HISI_VSYN HISI_PLK HISI_T0 HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T HISI_T0 HISI_T HISI_MLK SPI_NPS0 SPI_NPS SPI_NPS RT_WTEXT TIMER TIO0 EIM_EXTINT_ EIM_EXTINT_ EI_S0 EI_SWE EI_S EI_RS V. V. [0:] EI_NWIT EI_NWR0 EI_FRNW EI_NNOE EI_NNWE EI_0 EI_ EI_SS TWI_T TWI_LK V. R0 k V. V. J - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V. EI_FE[:] EI_[0:] EI_[0:] EI_NS[0:] TMEL S Vestre Rosten N-0 TILLER TSTK000 - PI connector Size ocument Number Rev T0
V. V. 00 00n 0 00n 0 00n 0 00n 0 00n 0 00n 0 00n 0 0 uf 0 0 uf 0 0 uf 0 00n 00n 00n 00n 00n 00n 00n 00n 00n 00n 0 00n 00n 00n 00n 00n 00n 00n 00n 00n 00n 00n 0 00n 00n 00n 00n 0 00n 0 uf 0 uf 0 uf 0 uf 0 uf 0 uf V. 00n 00n 00n 00n 00n 0 uf TMEL S Vestre Rosten N-0 TILLER TSTK000 - ecoupling Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
NOTE: Power on sequece is : V, followed by.v, followed by.v, followed by.v V. J00 00 X V. V. V. V. POWER TEST POINTS V. Switch ON when ctuator in UP position J -0- J T000/ SW00 switch MRS0TG ETMVQE 0 0 0 uf uf uf F SM00F 0 uf uf VIN uf 0n 0 U0 VIN SWITH VIN SWITH SWITH ON/OFF N N F N N N P LMS-.0/NOP IN_ 0n L MSS-ML u MRS0TG u u PG_ U VIN VOUT S ERROR LPES-. R 00k PG_V. V. uf V Regulator.V Regulator u u R 0k R0.k R k u.n n n L R k R 0k R 0k IN_ MSS0-NL U OMP VREF F VO VTJ TM SEL LX LX 0 LX LX LX LX N ELREZ S OS STN STP EN PG V VIN VIN 0 VIN P P P N.V Regulator 0p u 0n 0 u R 0k R.k 0 TS PG_ 0 u V. 0 u R 0k R.k R.k u 0 n n R0 k 0 n L ummy Load R k R 0k R 0k IN_V. MSS0-NL U OMP VREF F VO VTJ TM SEL LX LX 0 LX LX LX LX N ELREZ S OS STN STP EN PG V VIN VIN 0 VIN P P P N.V Regulator 0p u R 0k 0n 0 u TMEL S Vestre Rosten N-0 TILLER PG_V. PG_V. PG_V. POWER LE UE 0 SNT0R R 0R LE QTLP0TR NOTE: Separate S and P planes are placed on the P for U and U TSTK000 - Power Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
PS T 00n 0 00n 00n J KEYOR U PS LOK 00n SHIEL PS T URT N S J + V+ V 00n - V- PS LOK + N SL - SHN TTL/MOS RS- -- URT TX TIN TOUT URT RTS RTS TIN TOUT 0 URT TX RX TIN TOUT TS TX PS T ROUT 0 ROUT V URT 00n J SHIEL N V N -- MOUSE S SL PS T PS LOK PS LOK ROUT ROUT ROUT ROUT ROUT EN MXEEUI+ RIN RIN RIN RIN RIN 0 KFX-ES-NJ URT J URT RX TX Jumper Select for use of URT on or EXP_HR or PI 0 URT RX URT TS JP 00 X JP 00X _RX_MX _TS_MX _RX_EXPHR PI_RX _TS_EXPHR KFX-ES-NJ URT TX URT RX 0 uf 00n U VLE TX RX S SHIEL V N TM0/TR Jumper Select for use of URT on or EXP_HR URT RX JP 00X _RX_MX _RX_EXPHR TMEL S Vestre Rosten N-0 TILLER TSTK000 - Uarts Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of
L J VUS - + SHL SHL US_M US_P TP TP TP US_M US_P VUS - + SHIEL SHIEL J0 L US_VUS US_M US_P US_I V - + I SHIEL J TMEL S Vestre Rosten N-0 TILLER TSTK000 - US Size ocument Number Rev T0 ate: Tuesday, September, 00 Sheet of