ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation

Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive Noise! CLK Generation 2

Packaging Technology! Include important package related parasitics in the chip design and simulation " Package VDD and GND planes " On-chip VDD and GND busses " Bond wire lengths " On-chip inductive effects " Thermal resistance " Temp rise due to on-chip power dissipation " Package cost Penn ESE 570 Spring 2018 - Khanna 3

Package Bonding Techniques Penn ESE 570 Spring 2018 - Khanna 4

Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring 2018 - Khanna 5

Summary of Package Types 6

Variation and Testing

Modeling Process Variations + + + 8

Parametric Yield = = = = 9

Parametric Yield m τp = 0.184 ns σ τp = 0.023 ns 10

Parametric Yield Estimation Acceptable Region In Performance Space A r 2-dimensional space 0.5 = p-dimensional space 11

Parametric Yield Estimation Probability density functions (PDFs) for r k are usually not known specifically. Acceptable Region In Performance Space A r 2-dimensional space 0.5 p-dimensional space = Parametric yield is a scalar, deterministic quantity that is difficult to evaluate. 12

Parametric Yield Estimation = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. A x A x A x Parametric yield = = = 13

Parametric Yield Estimation = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. Parametric yield = A x = A x = A x 14

Parametric Yield Estimation Monte Carlo Simulations used to estimate PDFs of parameter values and estimate yield = = Acceptable circuit parameters for the design point d A x = Acceptable Region In Parameter Space A x d Allowed circuit parameter values restricted to subset of circuit parameter space due to physical considerations. Parametric yield = A x = A x = A x 15

Manufacturing Process Test dies on wafer Test packaged parts 16

Manufacturing Tests! Characterization Testing " Used to characterize devices and performed through production life to improve the process, hence yield! Production testing " Factory testing of all manufactured chips for parametric faults and for random defects. " The test patterns may not cover all possible functions and data patterns but must have a high fault coverage of modeled faults. " The main driver is cost, since every device must be tested. Test time must be absolutely minimized. " Only a go/no-go decision is made. 17

Testing Principle Device Under Test (DUT) 18

Observability & Controllability! Observability: measure of the ease of observing a node by watching external output pins of the chip! Controllability: measure of the ease of forcing a node to 0 or 1 by driving input pins of the chip! Good observability and controllability reduces number of test vectors required for manufacturing test " Reduces the cost of testing " Motivates design-for-test 19

Design For Test! Design the chip to increase observability and controllability " How to do for combinational logic? " Sequential logic? 20

Design For Test! Design the chip to increase observability and controllability " How to do for combinational logic? " Sequential logic?! If each register could be observed and controlled, test problem reduces to testing combinational logic between registers 21

Scan Based Testing! Scan test is to obtain control and observability for registers (eg. FFs) " It reduces sequential Test Pattern Generation circuits (TPG) to combinational TPG circuits! With Scan, a synchronous sequential circuit works in two modes. " Normal mode and Test mode: NORMAL TEST! In test mode, all FFs are configured as shift registers, with Scan-in and Scan-out 22

I(nput)/O(utput) Circuits

ESD Protection Human Body Model (HBM) Machine Model (MM) Electrostatic charge builds up and then discharges when a low-resistance path becomes available. 24

Lumped Circuit model of HBM and MM After exposure to the ESD waveform, a failed IC exhibits latch-up or fails one or more data sheet specifications. 25

ESD Protection Network V DD 26

Input Pad with Tristate Buffer TB 27

Output Pads CK CK D P N Z 1 1 0 0 1 = D 1 0 1 1 0 = D 0 x 1 0 HIGH Z 28

Output Pads MP1 MP2 CK = 0 => MN2 & MP2 OFF => Z = HIGH Z CK = 1 => MN2 & MP2 ON => Z = D MN2 MN1 29

Inductive Noise

LC Response! What happens here? ω = 1 LC V 2 V 2 = A + Be jωt V 2 = V + Be j! # " 1 CL $ & % t 31

LC Response! What happens here? ω = 1 LC V 2 V 2 = A + Be jωt V 2 = V + Be j! # " 1 CL $ & % t 32

Response? V 2 33

RLC Response $ # V 2 = V S + Be! For what R does this circuit oscillate? Decay Oscillation V 2 " " R % 2L & 't $ j e $ # 1 LC " R % $ ' # 2L & 2 % ' ' t & 34

RLC Response $ # V 2 = V S + Be! For what R does this circuit oscillate? Decay Oscillation V 2 " " R % 2L & 't $ j e $ # 1 LC " R % $ ' # 2L & 2 % ' ' t & 1 LC " R % $ ' # 2L & 1 LC > " $ # R 2L 2 % ' & 2 > 0 4L C > R 35

RLC Response (R=100) 36

RLC Response 37

Inductance of Wire 38

Inductance: Wire over Ground Plane A C = ε r ε 0 d = ε wl rε 0 h # L l µ 0µ h& % r ( $ w ' 39

Inductance: Wire over Ground Plane C' = ε r ε 0 w h " L' µ 0µ h % $ r ' # w & C'L' = εµ C and L per unit length L' = εµ C' 40

On Chip Inductance! C wire = 0.16 pf (for the 1mm)! C wire = 0.16nF/m! Permeability µ 0 µ Si02 =12.6 10-7 H/m! Permitivity ε ox =3.5 10-11 F/m L' = εµ C' 41

On Chip Inductance! C wire = 0.16 pf (for the 1mm)! C wire = 0.16nF/m! Permeability µ 0 µ Si02 =12.6 10-7 H/m! Permitivity ε ox =3.5 10-11 F/m! 276 ph (for 1 mm) L' = εµ C' 42

Inductors! Bond pads/wires! Package leads! Long wire runs! Cables Src: http://en.wikipedia.org/wiki/file:wirebonding2.svg 43

Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Penn ESE 570 Spring 2018 - Khanna 44

Where Inductive Noise Arises 45

Signal Path 46

Power Ground 47

Power Ground 48

RLC Response 49

How to Improve Inductive Noise 50

Minimize the L! Make wires short! Use power and ground planes " Think of power plane as a very wide wire # L l µ 0µ h& % r ( $ w ' 51

Flip Chip, Area IO http://www.izm.fraunhofer.de/en/abteilungen/high_density_interconnectwaferlevelpackaging/arbeitsgebiete/arbeitsgebiet1.html 52

Add Good C s! Bypass Capacitors inside the inductances " On board " On package " On chip 53

Bypass Capacitor Example 54

Bypass Capacitor Example No bypass cap No package inductance package inductance w/ bypass cap 55

Bypassed Supplies (@ transistor) 56

Bypassed Output 57

CLK Generation

Clock System Architecture Global Clock! Chip receives external clock through I/O pad or an internal clock is included in the Clock Generator.! Clock generator adjusts the global clock to the external clock.! Global clock is distributed across the chip.! Local drivers and clock gaters drive the physical clocks to clocked elements. 59

On-chip CLK Generation 60

Two-Phase CLK generation 61

Clock Skew and Jitter! Most systems distribute a global clock and then use local clock gaters located near clocked elements.! Clock should theoretically arrive simultaneously to all sequential circuits.! Practically it arrives in different times. The differences are called clock skews.! Skews result from paths mismatches, process variations and ambient conditions, resulting in physical clocks global clock. 62

Clock Skew Components! Systematic: skew exists under nominal conditions. It can be minimized by appropriate design.! Random: is variable skew caused by random process variations. It can be measured on silicon and adjusted by DLL components.! Drift: time-dependent skew caused by time-dependent environmental variations, occurring relatively slowly. Compensation of those must takes place periodically.! Jitter: is rapid clock edge changes, occurring by power noise and clock generator jitter. It cannot be compensated. Reference Edge Unit Interval Edge Location Shifted Ideal Edge Location 63

CLK Generation PLL Phase-locked loops Input Clock PD LF VCO Clock Distribution & Buffers Frequency/Phase Control Output Clock DLL Delay-locked loops Input Clock PD LF Variable Delay Line Delay Control Clock Distribution & Buffers Output Clock 64

Some Representative Clock Distribution Networks 65

Idea! Observability and Controlability reduce cost of testing and motivates design-for-test! I/O circuits attempt to interact with and isolate from external sources " ESD protection, level shifting " High impedence output! Inductive noise " Originates in signal paths and supplies " Minimize wires when possible and add bypass capacitors! CLK design and distribution is necessary for correct operation and timing 66

Admin! Final Project " Design memory (SRAM) " EC for best figure of merits (FOM = Area*Power*Delay 2 ) " Due 4/24 (last day of class) " Everyone gets an extension until 5/4 (day of final exam) " Absolutely doable by 2 people by 4/24 67