EECS150 - Digital Design Lecture 17 - Combinational Logic Circuits. Limitations on Clock Rate - Review

EECS150 - Digital Design Lecture 17 - Combinational Logic Circuits Finish off Timing First March 17, 2009 John Wawrzynek Spring 2009 EECS150 - Lec17-timing Page 1 Limitations on Clock Rate - Review 1 Logic Gate Delay 2 Delays in flip-flops What are typical delay values? Both times contribute to limiting the clock period. What must happen in one clock cycle for correct operation? All signals connected to FF (or memory) inputs must be ready and setup before rising edge of clock. For now we assume perfect clock distribution (all flip-flops see the clock at the same time). Spring 2009 EECS150 - Lec17-timing Page 2

In General... A For correct operation: Review: General C/L Cell Delay Model X T τ clk Q + τ CL + τ setup B Model:... MOS X How do Cout we enumerate all paths? X for all paths. X Any circuit input or register output functional (input to any -> output) register behaviorinput or circuit output? Note: transition Cout setup time for outputs is a function of what it connects to. Combinational clk-to-q Cell (symbol) for is circuit fully specified inputs depends by: on where it comes from. functional (input Spring -> 2009 output) behavior CS152 / Kubiatowicz EECS150 - Lec17-timing Page 3 B Spring 2004 1/28/04 UCB Spring 2004 - truth-table, logic equation, Lec3.29 VHDL OS Linear model composes 8/04 UCB Spring 2004 etal Oxide Semiconductor Semiconductor) transistors Semiconductor) transistors Symbol Circuit PMOS CL Delay: Transistors as water valves In Out In Out!"#$%&'(#)*(+,%-$*".(/0 Vdd = 5V If electrons are water molecules, Basic Components: CMOS 1 Inverter 2+.$0#$03 and a capacitor a bucket... e onductor Symbol te e h load factor of each input critical propagation delay from each input to each output for each transition In Combinational Logic Cell Vout Internal Delay A on p-fet fills Vdd = 5V In up the capacitor with charge. CS152 / Kubiatowicz Vout Lec3.31 Delay Va -> Vout Review: General C/L Cell Delay Model Combinational Cell (symbol) is fully specified by: X X delay per unit - load truth-table, logic equation, VHDL load factor of each input X critical propagation delay from each input to each output for each Ccritical - T HL (A, o) = Fixed Internal Delay + Load-dependent-delay x load Linear model composes Discharge 0 Vdd Vin Time Water level CS152 / Kubiatowicz 8/04 UCB Spring 2004 Spring 2009 EECS150 - Lec17-timing Lec3.32 Page 4 A B... Combinational Logic Cell - T HL (A, o) = Fixed Internal Delay + Load-dependent-delay x load Out 2+.$0#$03 Inverter Operation te onductor B Spring 2004 Vdd Open Charge Vout Cout Internal Delay 1/28/04 UCB Spring 2004 Vdd 1 Vdd Delay Va -> Vout Basic Components: CMOS Inverter Inverter Operation GND = 0v Vdd 1 Vdd Vout Circuit PMOS Vdd Out Charge!"#$%&'(#)*(+,%-$*".(/0 NMOS GND = 0v Open 0 Vdd 1 4546%,"#$3 A on n-fet empties the bucket. X CS152 / Kubiatowicz Lec3.30 Open Out This model is often good enough... Water level Vdd X X X X X delay per unit load X Time Vdd NMOS Vin Vdd Ccritical Cout CS152 / Kubiatowicz Lec3.30 Open Vdd Out Discharge CS152 / Kubiatowicz Lec3.32 4546%,"#$3!"#$%&'())* ++,!-.)'/ 012-)34$5$%& 67&1'-)

Gate Delay is the Result of Cascading Cascaded gates: transfer curve for inverter. Spring 2009 EECS150 - Lec17-timing Page 5 Delay in Flip-flops Setup time results from delay through first latch. clk clk clk Clock to Q delay results from delay through second latch. clk clk clk clk clk Spring 2009 EECS150 - Lec17-timing Page 6

Delay and Fan-out 2 1 3 The delay of a gate is proportional to its output capacitance. Connecting the output of gate one increases it s output capacitance. Therefore, it takes increasingly longer for the output of a gate to reach the switching threshold of the gates it drives as we add more output connections. Driving wires also contributes to fan-out delay. What can be done to remedy this problem in large fan-out situations? Spring 2009 EECS150 - Lec17-timing Page 7 Linear Delay Model Each input adds to output capacitance of previous module. Total output capacitance represented by C Total delay through the module: T = D + S * C, where D = the delay with no output load S represents the strength of the output drive C = total output capacitance. In reality, different delay from each input to each output, and different for different transitions (0 to 1 versus 1 to 0) on inputs and outputs. This model is hierarchically composable. Spring 2009 EECS150 - Lec17-timing Page 8

Searching for processor critical path Must consider all connected register pairs, paths from input to register, register to output. Don t forget the controller.? Design tools help in the search. Synthesis tools report delays on paths, Special static timing analyzers accept a design netlist and report path delays, and, of course, simulators can be used to determine timing performance. Tools that are expected to do something about the timing behavior (such as synthesizers), also include provisions for specifying input arrival times (relative to the clock), and output requirements (set-up times of next stage). Spring 2009 EECS150 - Lec17-timing Page 9 CLK CLK Clock Skew CL CLK CLK clock skew, delay in distribution If clock period T = T CL +T setup +T clk Q, circuit will fail. Therefore: 1. Control clock skew a) Careful clock distribution. Equalize path delay from clock source to all clock loads by controlling wires delay and buffer delay. b) don t gate clocks in a non-uniform way. 2. T T CL +T setup +T clk Q + worst case skew. Most modern large high-performance chips (microprocessors) control end to end clock skew to a small fraction of the clock period. Spring 2009 EECS150 - Lec17-timing Page 10

Timing in Xilinx Designs Spring 2009 EECS150 - Lec17-timing Page 11 From earlier lecture: Virtex-5 slice SLICE LUT O6 (D) 6-LUT delay is 0.9 ns (D[6:1]) 6 A[6:1] D Q (DQ) 1.1 GHz toggle speed (C[6:1]) (B[6:1]) 6 6 LUT O6 A[6:1] LUT O6 A[6:1] (Optional) (C) (CQ) D Q (Optional) (B) (BQ) D Q 128 x 32b LUT RAM access time is 1.1 ns 0.909 GHz toggle speed (A[6:1]) 6 A[6:1] LUT O6 (Optional) (A) (AQ) D Q But yet... (CLK) (Optional) Spring 2009 EECS150 - Lec17-timing Page 12

Xilinx CPU runs at 201 MHz... 4.5x ).0*1$%2(3#&4. slower 567!%&$!"#$!'()*+,)-.'/(-01 2+(3-')1*45,1 $+(!7 #*.8*59 :.+')1*!'()*+,)-.' $+441* MicroBlaze!'()*+,)-.' 61,.01 @00AB+2 BC-4)A%.8-,5< &+<)-D<E ;18-()1*37-<1 =>?=>2 65)5/(-01 2+(3-')1*45,1 $+(!7 6%&$ 6"#$ 2!"##"$%&'"%()%*"+%,-.'% / 0123%,-.4'%5*%65$#"7849%:!%4;< / 04<<%,-.2'%%5*%65$#"78=9%:!%=;< 2 )$(>%?%'#@A"%8B%=%'#@A"%C5C"D5*" 2 *"+%C$(E"''($F%)$(>%<;31% G:5C'H:IJ%#(%0;04%G:5C'H:IJ 2 0K<:IJ%8B%1<0%:IJ 2 022%8B%1?<%GL$M'#(*"%:5C' Comparison to Virtex 4 version Spring 2009 EECS150 - Lec17-timing Page 13 Major delay source: Interconnect Slices define regular connections to the switching fabric, and to slices in CLBs above and below it on the die. COUT COUT COUT COUT CLB COUT COUT CLB Slice X1Y1 CLB Slice X3Y1 Slice(1) Slice X0Y1 Slice X2Y1 Switch Matrix Slice(0) CLB CIN COUT CIN Slice X1Y0 COUT CLB CIN COUT CIN Slice X3Y0 COUT CIN CIN Slice X0Y0 Slice X2Y0 UG190_5_01_122605 UG190_5_02_122605 Spring 2009 EECS150 - Lec17-timing Page 14

Simplified model of interconnect... Wires are slow because (1) each green dot is a transistor switch (2) path may not be shortest length (3) all wires are too long! To this Connect this Delay in FPGA designs are particularly layout sensitive. Placement and routing tools spend most of there cycles in timing optimization. When Spring 2009 EECS150 - Lec17-timing Page Xilinx designs FPGA chips, wiring channels are optimized for (2) & (3). What are the green dots? Set during configuration. One flip-flop and a pass gate for each switch point. An on transistor adds resistance and capacitance to the wires it connects. An off transistor adds capacitance. In order to have enough wires in the channels to wire up CLBs for most circuits, we need a lot of switch points! Thus, 80%+ of FPGA is for wiring. Spring 2009 EECS150 - Lec17-timing Page 16

R More realistic Virtex-5 model... Performance Advantages for Functional Blocks "Free" Ground or V CC to initialize the carry function 1-hop wires to nearest neighbors The performance for arithmetic functions as measured by the path delay is significantly improved, as shown in Figure 7. 23)#$ %"4405# 1$!"( $)#*+% +$!"() 6$!"() Delay (ns) 4 3 2 Virtex-5 FPGAs 1st Ring WP246_04_050206 Virtex-5 Virtex-4 FPGAs 665 ps Design Examples performance and easier design routability. Essentially, the Virtex-5 family interconnect pattern provides fast, predictable routing based on distance. 2nd Ring 723 ps Figure 4 compares the delays incurred from a source register in one CLB driving a LUT packed with a second register in a surrounding CLB. The goal is to measure the effect of the incremental routing delays for both the Virtex-4 and Virtex-5 family WP245_04_050106 architectures. rtex-5 FPGAs R 5", % 1st Ring of CLBs 2nd Ring 8-b 16-b 32-b 64-b 8-b 16-b 2nd 32-b Ring of CLBs64-b Spring 2009 EECS150 - Lec17-timing WP245_07_051006 Page 17 Figure 4: Routing Delay Comparison for Virtex-4 and Virtex-5 FPGAs Multi-Bit Adder Timing Comparison for Virtex-4 and Virtex-5 FPGAs nce Advantages for Functional Blocks M Figure 7: 1 Design Examples The benefits of the new 6-input LUT architecture are detailed in the following examples. Table 2 shows a performance comparison of logic and Multiplexers arithmetic functions between the Virtex-4 and Virtex-5 families. Figures shown are for the fastest speed grade in each device family. Designs were run through ISE 8.1i software. Table 2: Performance Comparisons of Functional Blocks Barrel Shifter, 32-bit Performance 3.9Advantages ns for Functional Blocks 2.8 ns "Free" Ground or V CC to initialize the carry function The performance for arithmetic functions as measured by the path delay is significantly improved, as shown in Figure 7. 3 2 Spring 2009 8-b 16-b 32-b EECS150 64-b - Lec17-timing 8-b 16-b 32-b 64-b Page 18 The Virtex-5 Figure family 7: Multi-Bit block Adder RAM Timing can Comparison be operated for Virtex-4 in Simple and Virtex-5 Dual FPGAs Port mode to effectively double the block RAM bandwidth. Simple Dual Port mode allows the Performance Advantages for Functional Blocks CLB 1st Ring Virtex-4 751 ps 906 ps Virtex-5 665 ps 723 ps WP245_04_050106 One of the easiest examples is a multiplexer. A four-input LUT can implement a 2:1 MUX. Every multiplexer that has more than two inputs requires additional logic resources. A 4:1 MUX needs two 4-input LUTs and a MUXF in Virtex-4 architecture. With the new 6-input LUT, this 4:1 MUX is now implemented with a single LUT. An 8:1 MUX in a Virtex-4 device requires four LUTs and three MUXFs. With the new Virtex-5 family architecture, only two 6-input LUTs are required, resulting in better performance and better logic utilization. See Figure 5. 4 1. Virtex-5 FPGAs use one 6-input LUT and Virtex-4 FPGAs use two 4-input LUTs Virtex-4 FPGAs 6 www.xilinx.com WP245 (v1.1.1) July 7, 2006 Delay (ns) Virtex-5 FPGAs Virtex-4 FPGA The block RAM base size in the Virtex-5 family has increased to 36 Kbits (from 18 Kbits in the Virtex-4 family). This makes it easier to build larger memory arrays in 1 Virtex-5 devices. In addition, the 36 Kb block RAM can be used as two independent 18 Kbit block RAMs, hence, there is essentially no penalty for building many 18 Kbit or smaller RAM arrays on-chip. WP245_07_051006 Virtex-5 FPGA 6-Input Function (1) 1.1 ns 0.9 ns Adder, 64-bit 3.5 ns 2.5 ns Ternary Adder, 64-bit 4.3 ns 3.0 ns Magnitude Comparator, 48-bit 2.4 ns 1.8 ns LUT RAM, 128 x 32-bit 1.4 ns 1.1 ns Notes: Timing for small building blocks...

Clock circuits live in center column. 32 global clock wires go down the red column. Any 10 may be sent to a clock region. Also, 4 regional clocks (restricted functionality). CS 194-6 L6: Timing UC Regents Fall 2008 UCB!"#$%&'() Clocks have dedicated wires (low skew) GCLK7 GCLK5 GCLK6 GCLK4 4 4 BUFGMUX 4 DCM 4 4 DCM 4 8 Top Spine 8 8 8 Horizontal Spine Bottom Spine From: Xilinx Spartan 3 data sheet. Virtex is similar. 4 4 4 DCM 4 4 DCM 4 BUFGMUX Spring 2009 EECS150 - Lec17-timing Page 20 GCLK2 GCLK3 GCLK0 GCLK1

Die photo: Xilinx Virtex Gold wires are the clock tree. LX110T: 12 Digital Clock Managers (DCM) 6 Phase Locked Loops (PLL) 20 Clock I/O Pads CS 194-6 L6: Timing UC Regents Fall 2008 UCB!"#$%&'()

DCM: Clock deskew, clock phasing CLKIN CLKFB RST DCM_BASE CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED CLKIN 1 2 RST 3 Periods CLK0 CLK90 CLK180 CLKFX CLKFX180 CLKDV LOCKED LOCK DLL ug190_2_18_042406 Figure 2-17: RESET/LOCK Example How it works: Delay-line feedback CLKIN Variable Delay Line Control CLKOUT Clock Distribution Network IBUFG IBUF CLKIN CLKFB RST DCM_BASE CLK0 CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 BUFG OBUF CLKFB LOCKED Figure 2-3: Simplified DLL Circuit ug190_2_03_032506 Data Input Figure 2-8: Standard Usage ug190_2_08_032506 V CCO D FF Q Into the FPGA CLK Source IBUFG DCM CLKIN CLK0 CLKFB DCM Power Regulator V CCAUX Feedback Tap Delays System-Synchronous Source-Synchronous Default Setting Setting (Delay set to zero) Spring 2009 EECS150 - Lec17-timing Page 24 V CCINT ug190_2_04_042506

PLL: Frequency synthesis + de-jitter CLKIN1 CLKOUT0 CLKFBIN RST CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKFBOUT LOCKED 33 MHz Reference Clock M F VCO = F CLKIN! ---- D M F OUT = F CLKIN! -------- DO D = 1 O counters are shown in Figure PFD, CP, LF, VCO M = 16 D0=1 D0=2 D0=3 D0=4 D0=8 D=16 Power PC Core Power PC Gasket CLB/Fabric Memory Interface PCI 66 PCI 33 ug190_3_05_040906 PLL_BASE Clock Pin D PFD CP LF VCO O0 O1 M O2 O3 Spring 2009 EECS150 - Lec17-timing Page 25 O5 O4 Survey Results Spring 2009 EECS150 - Lec17-timing Page 26

Survey Results Late in getting homework and quiz solutions out (although, perhaps this is the norm for CS courses). We will work harder on this. Homework too long, often busy work. We made mistake early on of assigning too many redundant problems. Apparently not corrected yet. We will work to make homework more compact. Homework not relevant. By design, they often go beyond what we have time to talk about in class, and certainly at times are not related directly to the lab and project work. Spring 2009 EECS150 - Lec17-timing Page 27 Survey Results Labs good. Everyone seems to realizes that this is the first time for most of these. (Thanks for your understanding). Many people reported that lab 5 was too long. This was intentional. This was really a miniproject as opposed to the earlier labs. We should have given you more warning - sorry. Spring 2009 EECS150 - Lec17-timing Page 28

Survey Results Lecture and labs/project are disconnected. Not everything that is important to learn will show up in the labs and project. Homework is meant to focus on those topics - stuff from lecture that is normally covered in labs and project typically don't get attention in homework problems. In a similar vein, some people have the idea that the point of the class is only to teach you how to do the project. The project is just one element of learning the important topics in digital design. Spring 2009 EECS150 - Lec17-timing Page 29 Survey Results Feedback on the TAs is very positive. We re happy to hear this! Apparently Wawrzynek could improve his style of presentation to make it more interesting. I m happy to take suggestions. Spring 2009 EECS150 - Lec17-timing Page 30

Boolean Algebra I (Representations of Combinational Logic Circuits) Spring 2009 EECS150 - Lec17-timing Page 31 Outline Review of three representations for combinational logic: truth tables, graphical (logic gates), and algebraic equations Relationship among the three Adder example Laws of Boolean Algebra Canonical Forms Boolean Simplification Spring 2009 EECS150 - Lec17-timing Page 32

Combinational Logic (CL) Defined y i = f i (x0,...., xn-1), where x, y are {0,1}. Y is a function of only X. If we change X, Y will change immediately (well almost!). There is an implementation dependent delay from X to Y. Spring 2009 EECS150 - Lec17-timing Page 33 CL Block Example #1 Boolean Equation: y 0 = (x 0 AND not(x 1 )) OR (not(x 0 ) AND x 1 ) y 0 = x 0 x 1 ' + x 0 'x 1 Truth Table Description: Gate Representation: How would we prove that all three representations are equivalent? Spring 2009 EECS150 - Lec17-timing Page 34

Boolean Algebra/Logic Circuits Why are they called logic circuits? Logic: The study of the principles of reasoning. The 19th Century Mathematician, George Boole, developed a math. system (algebra) involving logic, Boolean Algebra. His variables took on TRUE, FALSE Later Claude Shannon (father of information theory) showed (in his Master s thesis!) how to map Boolean Algebra to digital circuits: Primitive functions of Boolean Algebra: Spring 2009 EECS150 - Lec17-timing Page 35 Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. How do we convert from one to the other? Spring 2009 EECS150 - Lec17-timing Page 36

CL Block Example #2 4-bit adder: Truth Table Representation: R = A + B, c is carry out In general: 2 n rows for n inputs. 256 rows! Is there a more efficient (compact) way to specify this function? Spring 2009 EECS150 - Lec17-timing Page 37 4-bit Adder Example Motivate the adder circuit design by hand addition: Add a1 and b1 as follows: Add a0 and b0 as follows: carry to next stage r = a XOR b = a b c = a AND b = ab r = a b c i co = ab + ac i + bc i Spring 2009 EECS150 - Lec17-timing Page 38

4-bit Adder Example In general: r i = a i b i c in c out = a i c in + a i b i + b i c in = c in (a i + b i ) + a i b i Now, the 4-bit adder: Full adder cell ripple adder Spring 2009 EECS150 - Lec17-timing Page 39 4-bit Adder Example Graphical Representation of FAcell r i = a i b i c in c out = a i c in + a i b i + b i c in Alternative Implementation (with 2-input gates): r i = (a i b i ) c in c out = c in (a i + b i ) + a i b i Spring 2009 EECS150 - Lec17-timing Page 40

Defined as: Boolean Algebra Spring 2009 EECS150 - Lec17-timing Page 41 Logic Functions Do the axioms hold? Ex: communitive law: 0+1 = 1+0? Spring 2009 EECS150 - Lec17-timing Page 42

Other logic functions of 2 variables (x,y) Look at NOR and NAND: Theorem: Any Boolean function that can be expressed as a truth table can be expressed using NAND and NOR. Proof sketch: How would you show that either NAND or NOR is sufficient? Spring 2009 EECS150 - Lec17-timing Page 43 Laws of Boolean Algebra Duality: A dual of a Boolean expression is derived by interchanging OR and AND operations, and 0s and 1s (literals are left unchanged). Any law that is true for an expression is also true for its dual. Operations with 0 and 1: 1. x + 0 = x x * 1 = x 2. x + 1 = 1 x * 0 = 0 Idempotent Law: 3. x + x = x x x = x Involution Law: 4. (x ) = x Laws of Complementarity: 5. x + x = 1 x x = 0 Commutative Law: 6. x + y = y + x x y = y x Spring 2009 EECS150 - Lec17-timing Page 44

Laws of Boolean Algebra (cont.) Associative Laws: (x + y) + z = x + (y + z) x y z = x (y z) Distributive Laws: x (y + z) = (x y) + (x z) x +(y z) = (x + y)(x + z) Simplification Theorems: x y + x y = x x + x y = x (x + y) (x + y ) = x x (x + y) = x DeMorgan s Law: (x + y + z + ) = x y z (x y z ) = x + y +z Theorem for Multiplying and Factoring: (x + y) (x + z) = x z + x y Consensus Theorem: x y + y z + x z = (x + y) (y + z) (x + z) x y + x z = (x + y) (x + z) Spring 2009 EECS150 - Lec17-timing Page 45 Proving Theorems via axioms of Boolean Algebra Ex: prove the theorem: x y + x y = x x y + x y = x (y + y ) distributive law x (y + y ) = x (1) x (1) = x identity complementary law Ex: prove the theorem: x + x y = x x + x y = x 1 + x y identity x 1 + x y = x (1 + y) distributive law x (1 + y) = x (1) identity x (1) = x identity Spring 2009 EECS150 - Lec17-timing Page 46

DeMorgan s Law (x + y) = x y Exhaustive Proof (x y) = x + y Exhaustive Proof Spring 2009 EECS150 - Lec17-timing Page 47 Relationship Among Representations * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. How do we convert from one to the other? Spring 2009 EECS150 - Lec17-timing Page 48

Canonical Forms Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. Two Types: * Sum of Products (SOP) * Product of Sums (POS) Sum of Products (disjunctive normal form, minterm expansion). Example: minterms a b c f f a b c 0 0 0 0 1 a b c 0 0 1 0 1 a bc 0 1 0 0 1 a bc 0 1 1 1 0 ab c 1 0 0 1 0 ab c 1 0 1 1 0 abc 1 1 0 1 0 abc 1 1 1 1 0 One product (and) term for each 1 in f: f = a bc + ab c + ab c +abc +abc f = a b c + a b c + a bc Spring 2009 EECS150 - Lec17-timing Page 49 Sum of Products (cont.) Canonical Forms are usually not minimal: Our Example: f = a bc + ab c + ab c + abc +abc (xy + xy = x) = a bc + ab + ab = a bc + a (x y + x = y + x) = a + bc f = a b c + a b c + a bc = a b + a bc = a ( b + bc ) = a ( b + c ) Spring 2009 EECS150 - Lec17-timing Page 50

Canonical Forms Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a b c f f a+b+c 0 0 0 0 1 a+b+c 0 0 1 0 1 a+b +c 0 1 0 0 1 a+b +c 0 1 1 1 0 a +b+c 1 0 0 1 0 a +b+c 1 0 1 1 0 a +b +c 1 1 0 1 0 a +b +c 1 1 1 1 0 One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c )(a+b +c) f = (a+b +c )(a +b+c)(a +b+c ) (a +b +c)(a+b+c ) Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. Spring 2009 EECS150 - Lec17-timing Page 51 Algebraic Simplification Example Ex: full adder (FA) carry out function (in canonical form): Cout = a bc + ab c + abc + abc Spring 2009 EECS150 - Lec17-timing Page 52

Algebraic Simplification Cout = a bc + ab c + abc + abc = a bc + ab c + abc + abc + abc = a bc + abc + ab c + abc + abc = (a + a)bc + ab c + abc + abc = (1)bc + ab c + abc + abc = bc + ab c + abc + abc + abc = bc + ab c + abc + abc + abc = bc + a(b +b)c + abc +abc = bc + a(1)c + abc + abc = bc + ac + ab(c + c) = bc + ac + ab(1) = bc + ac + ab Spring 2009 EECS150 - Lec17-timing Page 53