igitl Control o Electric rives Logic Circuits - Comintionl Boolen Alger, escription Form Czech Technicl University in Prgue Fculty o Electricl Engineering Ver.. J. Zdenek
Logic Comintionl Circuit Logic Comintionl Circuit (LCC) is deined y logic unction Inputs nd Outputs tke on only two possile vlues, or. y n y m At every time instnt vlues o ll output vriles re deined y vlues o input vriles only t the sme time instnt. (The LCC hs no memory, i.e. the LCC does not rememer its pst sttes) BEMEP igitl Control o Electric rives -
Logic Circuit Binry signls nd only igitl design igitl circuit logic circuit Logic circuit description Boolen lger, logic unctions igitl computer design generlly digitl system design esign o sic unctionl locks esign o inter-lock communiction Logic comintionl circuits (LCC) Logic sequentil circuits (LSC) LCC versus LSC LCC unction output depends on immedite unction input only LSO unction output depends on immedite inputs nd pst sttes (inner sttes) The ppliction o up-to-dt CA design tools (ls) BEMEP igitl Control o Electric rives -
esign prolems to e solved Function speciiction wht hs to e implemented? Hve to operte s deined in speciiction (irst ojective) esign optimliztion dierent spects (second ojective) Size Speed Power requirement Working conditions (temperture, virtion, ) Reliility Cost including design tools urtion o design phse Testility (T design or testility) BEMEP igitl Control o Electric rives -
Logic Comintionl Function Comintionl unction: yk (,,,..., n ), k,,..., m y y n y m BEMEP igitl Control o Electric rives -
igitl System esign Phses Speciiction Input nd output deinition Truth tles Boolen equtions Minimiztion esign t gte level HL - Hrdwre escription Lnguge Schem t gte level VHL, Verilog Hrdwre escription Lnguge Synthesis Behviourl (unctionl) simultion Post-route simultion igitl circuit implementtion esign veriiction Progrmmin g File Genertion BEMEP igitl Control o Electric rives -
Sotwre Hrdwre BASYS FPGA evice BEMEP igitl Control o Electric rives -
Boolen Alger Boolen lger inite set o elements which contins: logic vriles two inry opertion (logic conjuction nd disjunction) unry opertion negtion two logic sttes (logic constnts) Aioms:..,, c,... AN (.), OR ( ) NOT ( ),.. Aiom sttement without proo, it is considered s vlid BEMEP igitl Control o Electric rives - 8
Boolen Alger Lws:....... 8. 9.... ( ) c ( c) (. ). c.(. c).( c).. c (. c) ( )( c).... (. ).( )..( ). Commuttive Associtive istriutive Idempotency Complementrity Aggressivenes Neutrlity Asortion Negtion sortion Involution BEMEP igitl Control o Electric rives - 9
Lws:.. Boolen Alger.... c. c.. c ( ).( c).( c) ( ).( c) emorgn s Consensus sortion. (,, c,...). (,, c,...). (,, c,...) impliction (,, c,...). (, c,...). (, c,...) ecomposition (Shnnon s) Every logic unction cn e deined using only AN, OR nd NOT unctions ulity principle (emorgn s dulity):. Boolen lger is unchnged when ll dul pirs re interchnged. ( OR AN). ( AN OR) BEMEP igitl Control o Electric rives -
Gte Functions (Inverter) AN OR NOT written down AN. s : OR written down s : written down NOT s : BEMEP igitl Control o Electric rives -
Gte Functions NAN NOR XOR written down NAN. s : NOR written down s : written down XOR s : BEMEP igitl Control o Electric rives -
BEMEP igitl Control o Electric rives - Gte Functions (Multi-input devices) c c c AN OR XOR Odd numer o (Odd prity) c c c c
Generl Comintionl Gte, ely VIH VIL VOH VOL Comintionl gte description includes: Behviour (logic unction) Truth tle Logic eqution Outputs n-out (how mny net gtes inputs cn e connected to gte output) Propgtion ely (gte input to output signl time dely, to nd to trnsitions my hve dierent vlues) Input nd output nd logic levels (dierent technologies dierent levels) Power consumption Fstest nd smllest gtes (hve ewest trnsistors) re: inverter (NOT)(CMOS trnsistors), NAN NOR (), AN OR () tilh tihl BEMEP igitl Control o Electric rives -
Inde, Minterm, Mterm Truth tle ( c,, ) c,, Minterm (m) c.. c.. c.. c.. c.. c.. c.. c.. Mterm (M) c c c c c c c c Inde Independent vriles Minterms Functionl vlue Mterms n d i i... d d d... d d d i BEMEP igitl Control o Electric rives -
SoP nd PoS Stndrd Form SoP Sum-o-Products stndrd orm m i( ) m (,,, ) i ( c,, ) c.. c.. c.. c.. PoS Product-o-Sums stndrd orm Mj() M(,,, ) j ( c,, ) ( c ).( c ).( c ).( c ) BEMEP igitl Control o Electric rives -
Logic Function Minimiztion Why? Implementtion nd economic resons smller numer o gtes How? Minimiztion methods: ) Logic unction modiiction using oolen lger lws ) K-mp (Krnugh mp) ) Tle method connection o terms (Quine-McCluskey method) BEMEP igitl Control o Electric rives -
Logic Function Minimiztion (,, ) Minimlize unction with truth tle elow: m (,,,, ) SoP Sum o Products m(,,,, ) ) M (,, PoS Product o Sums M (,,) ( )( )( ) BEMEP igitl Control o Electric rives - 8
BEMEP igitl Control o Electric rives - 9 Logic Function Minimiztion ) ( ) ( ) ( ()() () () () () () ()() ()() ()() ()() ()() ( ) m( ) minterm( ) th solution ) Minimiztion using oolen lger lws:
BEMEP igitl Control o Electric rives - Logic Function Minimiztion ( ) m( ) minterm( ) nd solution ) ( ) ( ) ( () () () () () ()() ()() ()() ()() ()() ()() ) Minimiztion using oolen lger lws (cont.):
Logic Function Minimiztion ) Minimiztion using oolen lger lws (cont.): Two solutions: th solution nd solution Essentil prime implicnts hve to e included in solution BEMEP igitl Control o Electric rives -
BEMEP igitl Control o Electric rives - Logic Function Minimiztion ) Minimiztion using K-mps (Krnugh mp): ) m(,,,, th solution nd solution Compre with method )
Logic Function Minimiztion ) Tle method connection o terms (Quine-McCluskey) (Suitle or computer processing) m(,,,, ) (... ) (... ) (... )( ) (... Tle connection o terms ) m step m Step m step, () (,) - - () (,) - - () (,) - - () (,) - - () - - - - Minterm coverge Mrked lines were connected together nd resulting term ws got to net step BEMEP igitl Control o Electric rives -
Logic Function Minimiztion ) Tle method connection o terms (cont.): Tle connection o terms m Step m Step m Step, () (,) - - () (,) - - () (,) - - () (,) - - () - - - - Tle implicnts coverge Implicnts / m BEMEP igitl Control o Electric rives -
BEMEP igitl Control o Electric rives - Logic Function Minimiztion A B Implicnts / m ) Tle method connection o terms (cont.): Coverge tle evlution A B th solution nd solution Essentil prime implicnts hve to e included in solution Compre with methods ) nd ) th solution nd solution
BEMEP igitl Control o Electric rives - Logic Function Implementtion
BEMEP igitl Control o Electric rives - Logic Function Implementtion A NAN gtes only
BEMEP igitl Control o Electric rives - 8 Logic Function Implementtion ) )( ( B
BEMEP igitl Control o Electric rives - 9 Logic Function Implementtion ) ( ) ( ) ( ) ( ) ( ) ( ) ) ( ( B C NOR gtes only
BEMEP igitl Control o Electric rives - K-mp (Krnugh mp) K mp grphics representtion o truth tle Used or quick grphics minimiztion o logic unctions Only single input vrile chnges in djoining K-mp cells Overr ove relevnt K-mp re mens vrile vlue is K-mp cells numering (indeing) is suitle id or quick logic vlues trnser rom stndrd truth tle to K-mp K mp is pplicle or unctions with to () input vriles K - mp Truth tle Truth tle indeing () suitle id
K-mp, Minimiztion Procedure In K mp identiy n groups o djcent vlues (mrk ech group y ovl) Choose mimum re o s nd minimum numer o res elete vriles which in mrked re chnge vlue Vriles which does not chnge vlue in mrked re crete minimlized logic unction in SoP (Sum-o-Product) ormt (,,...) m (...,...,... ) BEMEP igitl Control o Electric rives -
BEMEP igitl Control o Electric rives - K-mp, Minimiztion Procedure XOR m(,) M (,) ) )( (
BEMEP igitl Control o Electric rives - K-mp, Minimiztion Procedure XOR ) )( ( M (,) m(,) ) ( ) ( ) )( ( ) )( (
K-mp, Minimiztion Procedure 8 9 8 9 BEMEP igitl Control o Electric rives -
K-mp, Minimiztion Procedure Ais o symmetry 8 9 8 9 9 8 BEMEP igitl Control o Electric rives -
K-mps Indeed Templtes 8 9 8 9 8 9 9 8 BEMEP igitl Control o Electric rives -
Logic Function Minimiztion Using K-mp or minimiztion o logic unction my e unsuccessull in some cses See net emple: Binry Adder BEMEP igitl Control o Electric rives -
Adder Wht? How to dd??? Result ormt? BEMEP igitl Control o Electric rives - 8
Adder Binry numers, How? inry Binry numer s BEMEP igitl Control o Electric rives - 9
Adder (Hl-dder) Binry numers (vriles), re single it now??? s Truth tle s s d Where is crry to higher order? BEMEP igitl Control o Electric rives -
Hl Adder Truth Tle nd Implementtion q s Hl Adder s m (, ) q m ( ) BEMEP igitl Control o Electric rives -
Full Adder p s q Crry rom lower order Crry to higher order BEMEP igitl Control o Electric rives -
BEMEP igitl Control o Electric rives - Full Adder Truth Tle nd SoP q s p p p p p s........ ),, m (, p p p p q........ ),, m (,
Full Adder No Minimiztion s.. p.. p.. p.. p SoP - no minimiztion, too comple circuit q.. p.. p.. p.. p BEMEP igitl Control o Electric rives -
Full Adder Attempt to Minimlize rom K-Mp Attempt to minimlize using K-mp s p s.. p.. p.. p.. p s.. p.. p.. p.. p No simpliiction q p q.. p.. p.. p.. p q. p. p. Prtilly simpliied BEMEP igitl Control o Electric rives -
Full Adder Logic unction modiiction using oolen lws XOR XNOR s.. p.. p.. p.. p p ( ) p ( ) p ( ) p ( ) p ( ) Hl Adder s XNOR XOR K-mp, choice o etter res q.. p.. p.. p.. p q p p p( ) p( ) q p Hl Adder q BEMEP igitl Control o Electric rives -
Full Adder using two hl dders BEMEP igitl Control o Electric rives -
Bit Full Adder - using our it ull dders BEMEP igitl Control o Electric rives - 8
Comintionl versus Sequentil Circuits Comintionl circuits At every time instnt vlues o ll output vriles re deined y vlues o input vriles only t the sme time instnt. (The LCC hs no memory, i.e. the LCC does not rememer its pst sttes). Sequentil circuits Output vriles depend on time sequence o input vriles. The sequentil circuit LSC hs memory, i.e. it rememer its pst sttes. Sequentil circuit ehviour is implemented y so clled closed loop principle. Mthemtic tools: Stte chrt, stte vrile, Logic unctions, ecittion unction, output unction, Finite Stte Mchine model (FSM) or Finite Stte Automton (FSA), Trnsition tle, Output tle. BEMEP igitl Control o Electric rives - 9
igitl Control o Electric rives Logic Circuits Comintionl Boolen Alger, escription Form EN Czech Technicl University in Prgue Fculty o Electricl Engineering