The MC03 is a quad two channel multiplexer with latch. It incorporates common clock and common data select inputs. The select input determines which data input is enabled. A high (H) level enables data inputs D00, D0, D0, and D30 and a low (L) level enables data inputs D0, D, D, D3. Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. P D = mw typ/pkg (No Load) t pd =. ns typ t r, t f =.0 ns typ (0% 0%) LOGIC DIAGRAM CDIP L SUFFIX CASE 0 PDIP P SUFFIX CASE 4 MARKING DIAGRAMS MC03L AWLYYWW MC03P AWLYYWW PLCC 0 FN SUFFIX CASE 03 AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week DIP PIN ASSIGNMENT TRUTH TABLE SELECT CLOCK Q0 n+ H L D00 L L D0 X H Q0 n Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page of the ON Semiconductor MECL Data Book (DL/D). ORDERING INFORMATION Device Package Shipping MC03L CDIP Units / Rail MC03P PDIP Units / Rail MC03FN PLCC 0 4 Units / Rail Semiconductor Components Industries, LLC, 00 January, 00 Rev. Publication Order Number: MC03/D
MC03 ELECTRICAL CHARACTERISTICS Characteristic Symbol Test Limits Pin Under 30 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E 3 3 madc Input Current I inh Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA Switching Times (0Ω Load) Propagation Delay Setup TIme Hold TIme 40 40 400 400 0 0 0 0 µadc I inl All 0. 0. 0.3 µadc t ++ t t ++ t Clock Input t + t Select Input t ++ t + t + t Select Input Select Input t setup t setup t hold t hold.00.00.0.0.00.00 0. 0. 0. 0........0 3.0.. 0.0 0.0.... 3. 3. 3. 3... 0.0 0.0.0.0 0.0 0.0.0.0.0.0...... 4. 4. 0.0 0.0.0.0.30.30 3. 3. 3. 3... 0.0 0.0.. 0.0 0.0 Rise Time (0 to 0%) t+. 4.0..0 3..4 4.0 Fall Time (0 to 0%) t. 4.0..0 3..4 4.0 *V ILmin applied to each input pin, one at a time......3.3.3.3.0 3.0.. 3. 3. 3. 3... 0.0 0..........4.4.....0 3.0.. 0.00 0.00.....3.3.3.3...... Vdc Vdc Vdc Vdc ns
MC03 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic @ Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE Symbol 30 C 0.0.0.0.00. + C 0.0.0.0.4. + C 0.00..03.440. Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current Output Voltage Logic V OH Output Voltage Logic 0 V OL Threshold Voltage Logic V OHA Threshold Voltage Logic 0 V OLA I inl All *, Switching Times (0Ω Load) +.V +0.3V Pulse In Pulse Out 3. V +.0 V Propagation Delay t ++ t t ++ t Setup TIme Hold TIme Clock Input t + t Select Input t ++ t + t + t Select Input Select Input t setup t setup t hold t hold Rise Time (0 to 0%) t+ Fall Time (0 to 0%) t *V ILmin applied to each input pin, one at a time. Each MECL 0,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.,,,,,, 3
MC03 PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 0 ISSUE C B N Y BRK U D L M Z W D X G V VIEW D D Z A R K H C G G E J T VIEW S VIEW S K F 4
MC03 PACKAGE DIMENSIONS T F A E G D PL B C N CDIP L SUFFIX CERAMIC DIP PACKAGE CASE 0 0 ISSUE T K L M J PL H A G B F C S K D PL T PDIP P SUFFIX PLASTIC DIP PACKAGE CASE 4 0 ISSUE R J L M
MC03 Notes
MC03 Notes
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