Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

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Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits Outline Examples - Identifying circuits from layouts - Identifying cross-sections corresponding to a layout - Extracting parasitics from layouts Summary Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-2 Example 1 Draw the schematic of the circuit corresponding to the CMOS layout. p+ Poly p-well n-substrate v in M2 M1 v out Fig. 210-02

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-3 Example 2 Draw the A-A cross-section to scale of the integrated layout shown. The approximate physical thicknesses are: n + diffusion = 0.5µm p + diffusion = 0.6µm p-well depth = 3µm Field oxide (FOX) = 4µm Polysilicon = 1µm = 1µm Thin oxide = 0.05µm Intermediate oxide () = 1µm (You may use square corners in the oxides and diffusions for purposes of simplicity.) See drawing. The scale for this drawing vertically is 0.25µm per square. A OUTPUT M M 2 1 GROUND F F F O O O X X X p+ p+ p+ p-well A' p+ Poly p-well n-substrate 1µm Fig210-03 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-4 Example 3 For the MOS transistors of Example 1, find the bulk resistances between the source and drain of each transistor to the metal. Assume that the sheet resistance of the is 35 Ω/sq. and of the p + is 80 Ω/sq. Number each MOSFET and use this number to identify your answers. To the metal means to the closest edge of the contacts. Therefore, the area of all sources and drains are the same, a rectangle which is 2µm by 11µm. Thus, R S1 = R D1 = (35Ω/sq.)(2/11) = 6.364 Ω and R S2 = R D2 = (80Ω/sq.)(2/11) = 14.546 Ω p+ Poly p-well n-substrate

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-5 Example 4 For the FETs of Example 1, find C GS, C GD, C BD, and C BS for each transistor. Assume that the voltage across the voltage dependent capacitors is zero and no channel is formed (cutoff). The various capacitances for this example are: Cox = 0.7fF/µm2 LD(NMOS) = 0.45µm LD(PMOS) = 0.6µm diffusion to p-well (junction, bottom) = 0.33fF/µm2 diffusion sidewall (junction, sidewall) = 0.9fF/µm p+ diffusion to substrate (junction, bottom) = 0.38fF/µm2 p+ diffusion sidewall (junction, sidewall) = 1.0fF/µm n-channel to bulk (junction, bottom) = 0.1fF/µm2 n-channel to bulk (junction, sidewall) = 0.3fF/µm p-channel to bulk (junction, bottom) = 0.1fF/µm2 p-channel to bulk (junction, sidewall) = 0.3fF/µm p+ Poly p-well n-substrate Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-6 Example 4 - Continued The area for all sources and drains is a rectangle 5µm by 11µm. Thus for M1, C GD1 = C GS1 = LD(NMOS)xWxC ox = 0.45µm 11µm 0.7fF/µm 2 = 3.465 ff C GD1 = C GS1 = 3.465 ff C BS1 = C BD1 =W L 0.33fF/µm 2 + 2(W+L)0.9fF/µm 2 = 5 11 0.33 + 32 0.9 = 18.15+28.8 = 46.95 ff C BS1 = C BD1 = 46.95 ff p+ Poly p-well n-substrate For M2, we get C GD2 = C GS2 = LD(PMOS)xWxC ox = 0.6µm 11µm 0.7fF/µm 2 = 4.62 ff C BS2 = C BD2 = W L 0.38fF/µm 2 + (2W+2L) 1.0fF/µm 2 = 5 11 0.38 + 32 1.0 = 20.9 + 32 = 52.9 ff C BS2 = C BD2 = 52.9 ff

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-7 Example 5 Draw the schematic of the circuit indicated below in the BJT layout and identify the collector, base and emitter terminals. Terminal 2 Terminal 1 Terminal 3 Fig. 210-05 emitter. p+isolation p base n-epitaxial Terminal 3 Fig. 210-04 Terminal 2 Terminal 1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-8 Example 6 Draw the A-A cross-section to scale. The approximate physical thicknesses are: n + emitter diffusion 1.3µm p-base diffusion 2.6µm n-epitaxial layer 10µm n + buried collector diffusion (not seen from the top view) - into the epitaxial layer 4µm and into the substrate 8µm All oxide and metal thickness are approximately 1µm. (You may approximate the oxides and diffusions with straight edges for simplicity.) See layout. A n-epi Terminal 3 emitter. A' p+isolation Terminal 2 Terminal 1 p+ p+ p+ p-iso n-epitaxial p-iso buried layer p-substrate n-epi p base n-epitaxial Fig. 210-06

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-9 Example 7 What is the resistance of the poly resistor shown if the sheet resistance is 30Ω/sq.? Polysilicon Polysilicon Corner squares should have 1/2 of the normal sheet resistance Fig. 210-07 1 1 1 1 1 1/2 1/3 1 1 1 1 1 1/2 Fig. 210-08 Resistance = (10squares + 0.5sq. + 0.5sq. + 0.33sq.)x30Ω/sq. = 339Ω Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-10 Example 8 A layout of two PMOS transistors both having a W/L of 20µm/2µm is shown. One of the layouts is concentric (M1) and the other is rectangular (M2). Find the value of C BD, C BS, C GD and C GS for both transistors. Assume zero-bias for any voltage dependent capacitors and that both transistors are saturated. Cox = 0.7fF/µm2 LD(NMOS) = 0.45µm LD(PMOS) = 0.6µm diffusion to p-well (junction, bottom) = 0.33fF/µm2 diffusion sidewall (junction, sidewall) = 0.9fF/µm p+ diffusion to substrate (junction, bottom) = 0.38fF/µm2 p+ diffusion sidewall (junction, sidewall) = 1.0fF/µm n-channel to bulk (junction, bottom) = 0.1fF/µm2 n-channel to bulk (junction, sidewall) = 0.3fF/µm p-channel to bulk (junction, bottom) = 0.1fF/µm2 p-channel to bulk (junction, sidewall) = 0.3fF/µm G1 D1 G2 S2 M1 M2 1 micron grid spacing S1 D2 p+ n-well Poly Contact

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-11 Example 8 Continued M1: A S1 = (15x15-7x7) = 176µ 2 A D1 = 3x3 = 9µ 2 P S1 = 4x15 + 4x7 = 88µ P D1 = 4x3 = 12µ C BD1 = 9µ 2 x0.38ff/µ 2 +12µx1.0fF/µ C BD1 = 15.42 ff C BS1 = 176µ 2 x0.38ff/µ 2 +88µx1.0fF/µ= 155fF C BS1 = 155 ff C GS1 = C ox W LD + 0.667C ox W L = 0.7fF/µ 2 28µ 0.6µ + 0.667 0.7fF/µ 2 20µ 2µ = 30.4 ff C GS1 = C GS2 = 30.4 ff C DG1 = 0.7fF/µ 2 12µ 0.6µ = 5.04 ff M2: A S2 = A D2 = 4x20 = 80µ 2, P S2 = P D2 = 4+4+20+2 = 48µ C BD2 = C BS2 = 80µ 2 x0.38ff/µ 2 +48µx1.0fF/µ = 78.4fF C BD2 =C BS2 =78.4 ff C DG2 = 0.7fF/µ 2 20µ 0.6µ = 8.4 ff C GS2 =0.7fF/µ 2 20 0.6µ 0.667 0.7fF/µ 2 20µ 2µ = 27.07 ff G1 D1 G2 S2 M1 M2 1 micron grid spacing S1 D2 p+ n-well Poly Contact Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-12 SUMMARY Understanding the physical layout of transistors and passive components is very important for analog integrated circuit design The physical perspective gives the designer a feeling for the parasitics associated with the active and passive components Extraction of these parasitics requires knowledge of the physical layout

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