Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1
Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages LOW, HIGH --> 0, 1 Negative logic -- seldom used Signal values denoted by variables (X, Y, FRED, etc.) Logic System Design I 4-2
Boolean operators Complement:X (opposite of X) AND: X Y OR: X + Y binary operators, described functionally by truth table. Axiomatic definition: A1-A5, A1 -A5 Logic System Design I 4-3
More definitions Literal: a variable or its complement X, X, FRED, CS_L Expression: literals combined by AND, OR, parentheses, complementation X+Y P Q R A + B C ((FRED Z ) + CS_L A B C + Q5) RESET Equation: Variable = expression P = ((FRED Z ) + CS_L A B C + Q5) RESET Logic System Design I 4-4
Logic symbols Logic System Design I 4-5
Theorems Proofs by perfect induction Logic System Design I 4-6
More Theorems Logic System Design I 4-7
N-variable Theorems Prove using finite induction Logic System Design I 4-8
DeMorgan Symbol Equivalence Logic System Design I 4-9
Likewise for OR Logic System Design I 4-10
DeMorgan Symbols Logic System Design I 4-11
Even more definitions (Sec. 4.1.6) Product term Sum-of-products expression Sum term Product-of-sums expression Normal term Minterm (n variables) Maxterm (n variables) Logic System Design I 4-12
Truth table vs. minterms & maxterms Logic System Design I 4-13
Combinational analysis Logic System Design I 4-14
Signal expressions Multiply out: F = ((X + Y ) Z) + (X Y Z ) = (X Z) + (Y Z) + (X Y Z ) Logic System Design I 4-15
New circuit, same function Logic System Design I 4-16
Add out logic function Circuit: Logic System Design I 4-17
Shortcut: Symbol substitution Logic System Design I 4-18
Different circuit, same function Logic System Design I 4-19
Another example Logic System Design I 4-20
Combinational-Circuit Analysis Combinational circuits -- outputs depend only on current inputs (not on history). Kinds of combinational analysis: exhaustive (truth table) algebraic (expressions) simulation / test bench Write functional description in HDL Define test conditions / test vecors Compare circuit output with functional description (or knowngood realization) Logic System Design I 4-21
Combinational-Circuit Design Sometimes you can write an equation or equations directly. Example (alarm circuit): Corresponding circuit: Logic System Design I 4-22
Alarm-circuit transformation Sum-of-products form Useful for programmable logic devices Multiply out : Logic System Design I 4-23
Sum-of-products form AND-OR NAND-NAND Logic System Design I 4-24
Product-of-sums form OR-AND NOR-NOR Logic System Design I 4-25
Brute-force design Truth table --> canonical sum (sum of minterms) Example: prime-number detector 4-bit input, N 3 N 2 N 1 N 0 F = Σ Ν3Ν2Ν1Ν0 (1,2,3,5,7,11,13) row N 3 N 2 N 1 N 0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 0 10 1 0 1 0 0 11 0 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 0 15 1 1 1 1 0 Logic System Design I 4-26
Minterm list --> canonical sum Logic System Design I 4-27
Algebraic simplification Theorem T8, Reduce number of gates and gate inputs Logic System Design I 4-28
Resulting circuit Logic System Design I 4-29
3-variable Karnaugh map Logic System Design I 4-30
3-variable Karnaugh map X Y Z X YZ XYZ XY Z X Y Z X YZ XYZ XY Z Logic System Design I 4-31
Visualizing T10 -- Karnaugh maps Logic System Design I 4-32
Visualizing T10 -- Karnaugh maps Logic System Design I 4-33
Example: F = Σ(1,2,5,7) Logic System Design I 4-34
Karnaugh-map usage Plot 1s corresponding to minterms of function. Circle largest possible rectangular sets of 1s. # of 1s in set must be power of 2 OK to cross edges Read off product terms, one per circled set. Variable is 1 ==> include variable Variable is 0 ==> include complement of variable Variable is both 0 and 1 ==> variable not included Circled sets and corresponding product terms are called prime implicants Minimum number of gates and gate inputs Logic System Design I 4-35
Prime-number detector Logic System Design I 4-36
Resulting Circuit. Logic System Design I 4-37
Another example Logic System Design I 4-38
Yet another example Distinguished 1 cells Essential prime implicants Logic System Design I 4-39
Another Example F(W,X,Y,Z) = Σm(0,1,2,4,5,6,8,9,12,13,14) Logic System Design I 4-40
Another Example F(W,X,Y,Z) = Σm(0,1,2,3,6,8,9,10,11,14) Logic System Design I 4-41
Another Example Logic System Design I 4-42
Don t Cares Copyright 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e (a) N 3 N 2 N 00 01 11 10 1 N 0 0 4 12 00 d N 1 01 11 10 1 3 2 5 7 6 13 1 1 d 1 1 1 15 d 14 d N 3 8 9 11 10 d d N 0 (b) N 3 N 3 N 2 N 1 N 0 00 01 11 10 N 00 d 3 N0 01 1 1 d N 1 11 1 1 d d 10 1 d d N 0 N 2 N 0 N 2 F = Σ N3,N2,N1,N0 (1,2,3,5,7) + d(10,11,12,13,14,15) N 2 N 1 N 2 F = N 3 N 0 + N 2 N 1 Logic System Design I 4-43
Another Example F(W,X,Y,Z) = Σm(0,1,2,3,6,8,9,10,11,14) + d(7,15) Logic System Design I 4-44
Current Logic Design Lots more than 6 inputs -- can t use Karnaugh maps Use software to synthesize logic expressions and minimize logic Hardware Description Languages -- VHDL and Verilog Logic System Design I 4-45