An Array-Based Test Circuit it for Fully Automated Gate Dielectric Breakdown Characterization John Keane, Shrinivas Venkatraman, Paulo Butzen*, and Chris H. Kim *State University of Rio Grande do Sul, Porto Alegre, Brazil University of Minnesota, Minneapolis 1
Outline of Presentation Introduction to Time Dependent Dielectric Breakdown (TDDB) Proposed TDDB Test Array Circuit Test Chip Calibration Breakdown Measurement Results Conclusions 2
Introduction to TDDB Traps generated under the influence of electric field Traps overlap Conductive path between gate and substrate Gate dielectric no longer a reliable insulator Parametric or functional failure 3
Progressive Dielectric Breakdown Ultra-thin dielectrics can experience soft breakdown without failing Focus shifts to monitoring current after 1st breakdown Designers & reliability engineers must settle on reliability metrics for circuits with different sensitivities A. Kerber, et al., IRPS, 2007 J. Stathis, CICT, 2005 4
TDDB Impact on Digital Circuits Decreased performance & reliability, increased leakage, or outright failure Reduced O/P swing in digital logic can be restored in subsequent stages, but speed suffers SRAM SNM is degraded as a function of BD location R. Rodriguez, et al., IEDL, 2003 R. Rodriguez, et al., IEDL, 2002 5
Statistical Characterization of TDDB Slope = β BD BD BD BD Breakdown related to generation of traps Deterministic : trap generation rate Statistical ti ti : critical trap density required for breakdown Failure statistics follow Weibull Distribution 1000s of sampled needed to characterize distribution E. Wu, et al., IBM J. of R & D, 2002 6
TDDB Lifetime Prediction Classical Reliability Approach Extrapolate stress results with respect to: Operating Conditions based on acceleration models Larger Chip Areas based on Poisson area scaling Lower Percentiles based on Weibull distribution Today consider unique environmental variables 1st failure may not lead to chip failure, etc... G. Groeseneken, et al., IPFA 2007 7
Prior TDDB Measurement Methods Individual device probing with expensive wafer probes; continuously monitor I GATE or V GATE of a single Device Under Test (DUT) per stress experiment. Karl proposed p a method to monitor the increase in gate leakage of a pair of DUTs whose gate voltage controls the frequency of a Schmitt Trigger Oscillator (ISSCC, 2008) 8
Proposed TDDB Measurement System FSM Row Periphe erals row<0:31 > Bitline COMPLETE E SCANOUT 32x32 array of stressed NMOS transistors Gate currents (I G ) measured with A/D current monitor and on-chip control logic 16b results scanned out and stored for post-processing Efficient collection of failure statistics by running a simple control program 9
TDDB Stress Cell Design col<m> I/O device core device VSTRESS FRESH Q VSTRESS D Q SEL DFF VSTRESS VSTRESS Q VSTRESS VCC Q row<n> SEL Stressed Device Facilitates accelerated stressing of the DUTs by using thick oxide I/O transistors in the supporting circuitry row<n> and col<m> signals used to select one cell FRESH signal used to gate off stress in any cell(s) 2 transmission gates cut off bitline leakage G 10
I G in stress cell A/D Current Monitor PRECHARGE V COMP V REF Analog Block I REF CLK MEASURE VCO 16b Counter Digital Block 16b Shift Register SCAN OUT Comparator output drops when V COMP falls to V REF Discharge rate is determined by I G plus I REF 16 bit counter runs at rate set by a VCO Less I G translates to a higher count result 11
Test Chip Implementation Technology 0.13µm CMOS Digital Supply 1.2V Dimensions 2 952x865µm2 Gate Resisistance Measurement Range ~1kΩ + Measurements automated with LabVIEW and a National Instruments t data acquisition iti board 12
Measurement Array Calibration COMP REF REF Ou utput Coun nt Result 1E+5 1E+05 1.E+05 1E+4 1.E+04 1E+3 1E+03 1.E+03 1E+2 1.E+02 1E+1 1.E+01 VCO Freq 0.90GHz 30ºC Count increases with decreasing discharge current EXT 1E+0 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 External Resistor (ohms) 1.E+00 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Obtain final count vs. total discharge path resistance characteristic with adjustable R EXT while A/D monitor is isolated from the array Subsequent measurement results translated into gate path resistance (R GATE ) by using this calibration curve R TOTAL = R EXT R GATE (R EXT fixed during measurements) 13
TDDB Array Measurement Issues 1E+07 1.E+07 100 Rmeasured MEASURE ED (ohms) 1.E+06 1E+05 1.E+05 1.E+04 1.E+03 1.E+02 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 R GATE (ohms) 80 60 40 20 0 GATE/Rmeasu red error E MEASUR RED RG GATE A) IG (A Resistance of transmission gates on measurement path not accounted for in calibration Error < 1.4% for R GATE of 240kΩ+; I G up to 5μA at 1.2V. Small error in progressive breakdown (PBD) region Device probing measurements show hard BD at our stress voltage levels of interest with ~4Hz sampling 14
Broken % of Gates Measured T BD Distributions 120% 2 100% 80% 60% 40% 20% Stress Voltage 4.2 4.0 3.8 4.3 4.1 3.9 o 0% -5 1E-1 1.E+001E+0 1.E+011E+1 1.E+021E+2 1.E+03 1E+3 1.E+04 1E+4 1.E+05-1 1 3 5 7 9 11 13 T BD or T FAIL (s) BD FAIL T BD or T FAIL (ln(s)) CDFs of T BD for a range of stress voltages Standard percentage scale (left), and Weibull scale (right) The Weibull slope factor (β) for 4.2V stress was 1.443 Slightly decreases for lower VSTRESS; increases at 4.3V Array-based design allows us to define an accurate CDF with a single test -F)) ln(-ln(1 1 0-1 -2-3 -4 15
TDDB Measurement Results 1E+05 1.E+05 1.E+04 1.E+04 1E+03 1.E+03 1.E+03 BD 1.E+02 1E+01 1.E+01 1.E+00 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 BD 1.E+02 1.E+01 2.6E-03 2.8E-03 3.0E-03 3.2E-03 3.4E-03 Exponential relationship of characteristic life with voltage In 30 O C to 100 O C range, TDDB follows Arrhenius behavior Careful studies of voltage and temperature acceleration required, particularly in advanced processes, where there has been some debate due to differing results 16
TDDB Area Scaling TBD at 63 3% (a.u.) BD Select smallest T BD from cluster of adjacent DUTs Measured results match well with the weakest-link theory Helps justify the use of Weibull statistics Can be used to determine β with fewer experiments Do stress experiments on DUTs with large area ratio Low sensitivity to statistical variation 17
Measured T BD Spatial Distribution ln(-ln(1- -F)) 3 2 1 0-1 -2-3 -4-5 -6 0 2 4 6 8 T BD or T FAIL (sec) Array format facilitates study of any spatial correlation 4 diagrams correspond to 4 divisions of the CDF, each representing 25% of the cells in a 20x20 array. No spatial correlation was detected 18
Conclusions Implemented a 32x32 array of TDDB test cells for efficient characterization of T BD statistics Stress cell design presented to avoid aging in supporting circuitry 16b result easily stored in spreadsheet for processing Reduces test time by a factor proportional p to # of DUTs Design is capable of tracking R GATE progression with 1.4% error up to the onset hard breakdown Measurement results from a number of stress conditions demonstrate circuit flexibility 19