Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with similar per Micetek suggestion dded a Jumper on S WR per U request ate //0 //0 //0 pproved ESIGNER X Replaced S part with shorter one //0 X Replaced S/MM connector 0/0/0 Released to Fab 0//0 dd J, J and J per customer req Released to fab 0//0 Replace with alternate part LEs //0 Microcontroller Solutions Group 0 William annon rive West ustin, TX - This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. IP lassification: FP: _ PUI: _ esigner: rawing Title: Rodolfo G rawn by: Rodolfo G Table of contents pproved: Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
. Unless Otherwise Specified: ll resistors are in ohms, %, / Watt ll capacitors are in uf, 0%, 0V ll voltages are ll polarized capacitors are aluminum electrolytic. Interrupted lines coded with the same letter or letter combinations are electrically connected.. evice type number is for reference only. The number varies with the manufacturer.. Special signal usage: _ enotes - ctive-low Signal <> or [] enotes - Vectored Signals. Interpret diagram in accordance with merican National Standards Institute specifications, current revision, with the exception of logic block symbology. IP lassification: FP: PUI: rawing Title: NOTES Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
Pg F_[:0] F_[:0] U F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 0 IO IO IO IO IO IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO 0 IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO 0 IO 0 0 0 F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_0 F_0_ F_R/W_ R 0K F_[:0] F_0_ Pg F_R/W_ Pg F_LE/F_S_ F_[:0] Pg efault: Shunted F_S0_ Pg Pg J HR X TH EPM0GT00N HR TH X J U IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 0 0 IO IO IO 0 IO IO IO IO IO IO F_IOR_ IO F_IOWR_ IO IO IO IO IO IO IO IO IO IO IO IO IO IO 0 IO IO IO IO IO IO IO IO 00 0 00 F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_OE_ F_WIT_ F_REG_ F_E_ F_WE_ F_ F_ F_REY F_RST_ F_[0:0] + 0.UF 0uF F_ F_ F_E_ F_OE_ F_WE_ F_REY F_RST_ F_REG_ J V V E E OE WE RY/SY SEL RESET REG 0 0 0 0 F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_[0:0] EPM0GT00N J IO IO IO IO IO 0 IO IO 0 IO IO GLK 0 IO IO IO IO IO IO IO IO IO GLK0 F_IOR_ F_IOWR_ F_WIT_ 0 0 IOR IOWR V V VS 0 VS WIT INPK 0 F ONNETOR 0 F_ F_ F_ F_ F_ F_ F_ F_0 F_[:0] F_[:0] Pg HR_X 0.UF NP PL ONNETIONS F HEER Pg Pg F_LK GLK0 GLK F_LK U GLK0/IO GLK/IO GLK/IO GLK/IO INT INT 0 IO IO 0 IO IO IO IO VIO_ VIO_ VIO_ VIO_ VIO_ VIO_ VINT VINT 0 _ TO_ TI_ TK_ IO /EV_OE IO /EV_LR TO TI TK F_OE_ RST_ 0.UF F_OE_ RST_ 0.UF 0.UF 0.UF + 0.UF 0.UF 0uF Pg Pg 0 + 0.UF 0.UF 0uF U VV VOUT VIN T + 0uF 0.UF LS 0.UF J F_ F_ F_ F_0 0 F_IOR_ F_IOWR_ F_WE_ F_REY F_ 0 F_RST_ F_WIT_ F_ F_0 F_ 0 F_ F_ F_ F_E_ F_OE_ F_ F_ F_ F_ F_ F_ F_ F_REG_ F_0 F_ F_ EPM0GT00N 0.UF J 0 HR X R K R K TK TO TI TO TI TK HR_X JTG[:] J JTG[:] Pg JTG JTG JTG JTG PL EOUPLING & JTG HR_X NP OPTIONL WIRE WRP HEERS IP lassification: FP: PUI: rawing Title: F & PL Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
00 0.UF 0 + 0 0.UF 0uF efault: Open F_S0_ HR X TH F_R/W_ S_R_ET S ET J HR X TH J0 F_[:0] S_PU R 0K J HR X TH S ET_J R 0K R 0K F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_OE_ F_0 F_0_ R 0K R0 0K S_PU R0 0K S_M/MOSI S_[0]/MISO S_[] S_[] R0 R0 0K R0 0K 0K 0 0 0 U 0 0 E G W U L J0 P_ P_ V V mraa VSS VSS S/MM SKT QL0 QL QL QL QL QL QL QL QU QU QU0 QU QU QU QU QU U? MRYS F_0 F_ F_ F_ F_ F_ F_ F_ S_PU S_PU S_PU S_PU S_SEL S_[] S_SEL S_[] _IRQ _IRQH S_R_ET LK M T0 T T T V 0 0 N S_LK/SLK S_M/MOSI S_[0]/MISO S_[] S_[] S_[]/S F_[:0] MRM J 0 JTG GPIO IRQ IRQH HR_X efault:, R00 00K efault: Open Pg F_[:0] S_LK/SLK S_[]/S J HR TH X efault:, JTG GPIO JTG F_LK Pg F_LK LKOUT0 J efault:, HR TH X Pg F_LE/F_S_ F_S0_ Pg F_S0_ F_ F_ F_ F_ F_ F_R/W_ Pg F_R/W_ F_OE_ F_ Pg F_OE_ F_[:0] F_ F_ F_ F_ F_ F_ F_0 S_M/MOSI S_[0]/MISO LKOUT SF_MISO SF_MOSI SF_S SF_S SF_LK GPIO IRQH IRQ 0 0 0 0 0 0 0 0 J00 V.V_ ELE_PS_SENSE _ SPI_LK/SH_LK SPI_S_/SH_ SPI_S0_/SH_ SPI_MOSI/SH_M SPI_MISO/SH_0 ETH_OL_ ETH_RXER_ ETH_TXLK_ ETH_TXEN_ ETH_TXER_ ETH_TX_ ETH_TX_ ETH_TX_ ETH_TX0_ GPIO/RTS GPIO/SH_ GPIO LKIN0 LKOUT _ N N N N _ TMR TMR GPIO.V_ PWM PWM PWM PWM NRX0 NTX0 WIRE SPI0_MISO SPI0_MOSI SPI0_S0_ SPI0_S_ SPI0_LK _ SL S GPIO/S_R_ET US0_P_POWN US0_M_POWN IRQ_H IRQ_G IRQ_F IRQ_E IRQ_ IRQ_ IRQ_ IRQ_ EI_LE/EI_S_ EI_S0 EI_ EI_ EI_ EI_ EI_ EI_R/W_ EI_OE_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 _.V_ V.V_.V 0 _ SL0 S0 GPIO/TS GPIO/SH_ GPIO/S ET ETH_RS ETH_M_ ETH_MIO_ ETH_RXLK_ ETH_RXV_ ETH_RX_ ETH_RX_ ETH_RX_ ETH_RX0_ SSI_MLK SSI_LK SSI_FS SSI_RX SSI_TX _ N N N N0 _ 0 TMR GPIO.V_ PWM PWM PWM PWM0 RX0 TX0 RX TX GPIO0 GPIO GPIO GPIO _ GPIO GPIO GPIO GPIO US0_M US0_P US0_I US0_VUS TMR TMR TMR TMR RSTIN_ RSTOUT_ LKOUT0 _ EI_ EI_ EI_ EI_ EI_0 EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_ EI_0 _.V_ 0 0 0 0 0 0 0 0 JTG JTG S ET RST_ LKOUT0 RST_ F_ F_ F_ F_ F_0 F_ F_ F_ F_ F_ F_ F_ F_ F_ F_0 JTG JTG JTG JTG Pg VV F_[:0] F_ F_ F_ Pg F_ F_ R0.0K JTG[:] GREEN F_[:0] R0 0 JTG[:] Pg R 0 RE LE Q00 MMT0LTG Pg PI EXPRESS X 0 + 0.uF J HR TH X S SOKET 0.UF SF_ R0 R 0K 0K HOL 0.UF V U S SO SI SK R 0K SF_MISO SF_MOSI SF_LK Note: While using GPIO control for HOL, ascertain to free up other GPIO connections on other Stories. SF_ GPIO efault:, J HR X SF_S SF_S HR TH X J Pg F_0_ F_0_ U V N Y 0.UF SNLVG0 F_0 PRIMRY PORT ONNETIONS TF0-SU IP lassification: FP: PUI: rawing Title: MRM, S & SFLSH Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of
0 J00 V.V_ ELE_PS_SENSE _ SPI_LK SPI_S_ SPI_S0_ SPI_MOSI SPI_MISO V.V_.V _ SL S GPIO ULPI_STOP ULPI_LK 0 0 0 0 0 0 0 0 ETH_OL_ GPIO ETH_RXER_ ETH_M_ ETH_TXLK_ ETH_MIO_ ETH_TXEN_ ETH_RXLK_ GPIO ETH_RXV_ GPIO/SH_ GPIO/SH_ GPIO0/SH_ GPIO/SH_ ETH_TX_ ETH_RX_ 0 ETH_TX0_ ETH_RX0_ ULPI_NEXT/US_M ULPI_T0/US_M ULPI_IR/US_P ULPI_T/US_P ULPI_T/US_M ULPI_T/US_M ULPI_T/US_P ULPI_T/US_P ULPI_T ULPI_T _0 _ L_HSYN/L_P N L_VSYN/L_P N0 N N 0 N N L_LK/L_P GPIO TMR TMR TMR GPIO GPIO0.V_.V_ PWM PWM PWM PWM0 PWM PWM 0 PWM PWM NRX RX/TSI0 NTX TX/TSI GPIO RTS/TSI L_OE/L_P TS/TSI L_0/L_P0 RX/TSI L_/L_P TX/TSI L_/L_P RTS/TSI L_/L_P TS/TSI 0 0 GPIO L_/L_P GPIO L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P IRQ_P/SPI_S_ L_/L_P IRQ_O/SPI_S_ L_0/L_P0 IRQ_N L_/L_P IRQ_M TMR IRQ_L TMR 0 IRQ_K TMR IRQ_J TMR IRQ_I L_/L_P L_/L_P L_/L_P L_/L_P L_/L_P EI_0/L_P EI_E/L_P EI_/L_P EI_E /L_P EI_/L_P EI_E /L_P0 EI_/L_P EI_E 0_/L_P 0 EI_/L_P EI_TSIZE0/L_P EI_/L_P EI_TSIZE/L_P EI_/L_P EI_TS_/L_P EI_/L_P EI_TST_/L_P EI_/L_P0 EI_T_/L_P EI_/L_P EI_S_/L_P EI_0/L_P EI_S_/L_P EI_/L_P EI_S_/L_P L_0/L_P0 EI_S_/L_P0 L_/L_P GPIO/L_P 0 L_/L_P L_/L_P.V_0.V_ TP PI EXPRESS X SEONRY PORT IP lassification: FP: PUI: rawing Title: OPTIONL PORT Size ocument Number Rev SH- PF: SPF- Friday, January, 00 ate: Sheet of