Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1
Noise in Digital Integrated Circuits Topic 4-2
DC Operation: Voltage Transfer Characteristic Consider a simple inverter When Vin = 0 Vout = Vdd When Vin = Vdd Vout = 0 In between, V out depends on current through transistors as determined by transistor width and length By KCL, steady state condition is: I dsn = I dsp Find transfer function by solving equations, but better insight using graphical method Topic 4-3
DC Transfer Curve: Load line Topic 4-4
DC Transfer Curve Topic 4-5
Operating Regions Topic 4-6
Effect of beta ratio on switching thresholds Extract switching point depends on β p / β n If β p / β n = 1, switching occurs at around Vdd/2 Otherwise: Topic 4-7
Noise Margins Topic 4-8
Maximize Noise Margins Select logic levels at unity gain point of DC transfer characteristic Topic 4-9
Voltage Transfer Characteristic of Real Inverter Topic 4-10
The Regenerative Property Topic 4-11
Delay Definitions Topic 4-12
Ring Oscillator Topic 4-13
Power Dissipation Topic 4-14
Delay Estimation Need to estimate delay without circuit simulation e.g. SPICE Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R so that t pd = RC Characterize transistors by finding their effective R depends on average current as gate switches Topic 4-15
RC Delay Models For each MOS transistor Assume ideal switch + capacitance + ON resistance Unit nmos has resistance R, gate capacitance C Unit pmos has resistance 2R, gate capacitance C Capacitance width ON resistance 1/width Topic 4-16
Computing the Capacitances Topic 4-17
Computing the Capacitances Topic 4-18
Impact of Rise Time on Delay Topic 4-19
Delay as a function of V DD Assuming Vdd = 5V Topic 4-20
Where Does Power Go in CMOS? Dynamic power charging and discharging capacitors Short circuit currents short circuit path between power rails during switching Leakage power Leaking diodes and transistors Topic 4-21
Dynamic Power Dissipation Vdd Vin The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. Topic 4-22
Short Circuit Currents Topic 4-23
Leakage Topic 4-24
Sub-Threshold in MOS Topic 4-25
How to reduce power? Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages (0.6 0.9 V by 2010!) Maintaining performance by threshold scaling leads to increased leakage Reduce switching activity Reduce physical capacitance Topic 4-26