74AHC2G126; 74AHCT2G126

Similar documents
2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

2-input EXCLUSIVE-OR gate

74AHC1G00; 74AHCT1G00

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

The 74LV08 provides a quad 2-input AND function.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

74AHC1G14; 74AHCT1G14

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

The 74LVC1G02 provides the single 2-input NOR function.

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

The 74LV32 provides a quad 2-input OR function.

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC1G125; 74HCT1G125

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

Octal bus transceiver; 3-state

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

The 74LVC1G11 provides a single 3-input AND gate.

Dual buffer/line driver; 3-state

74AHC2G241; 74AHCT2G241

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

Dual buffer/line driver; 3-state

74HC2G08-Q100; 74HCT2G08-Q100

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

74HC2G125; 74HCT2G125

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

Dual 2-to-4 line decoder/demultiplexer

74LV General description. 2. Features. 8-bit addressable latch

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

74HC238; 74HCT to-8 line decoder/demultiplexer

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC1G02-Q100; 74HCT1G02-Q100

74AHC1G125; 74AHCT1G125

Octal D-type transparent latch; 3-state

74AHC1G126; 74AHCT1G126

74HC1G32-Q100; 74HCT1G32-Q100

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

74HC1G125; 74HCT1G125

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC03-Q100; 74HCT03-Q100

74LVU General description. 2. Features. 3. Applications. Hex inverter

8-bit binary counter with output register; 3-state

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

The 74HC21 provide the 4-input AND function.

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74HC30-Q100; 74HCT30-Q100

Single supply translating buffer/line driver; 3-state

Octal buffer/line driver; 3-state

74HC154; 74HCT to-16 line decoder/demultiplexer

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

Hex inverter with open-drain outputs

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

The 74LV08 provides a quad 2-input AND function.

2-input single supply translating NAND gate

74HC594; 74HCT bit shift register with output register

Dual bus buffer/line driver; 3-state

Dual JK flip-flop with reset; negative-edge trigger

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14.

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs

Bus buffer/line driver; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state

5-stage Johnson decade counter

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

BCD to 7-segment latch/decoder/driver

74HC151-Q100; 74HCT151-Q100

NXP 74HC_HCT1G00 2-input NAND gate datasheet

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74AHC541-Q100; 74AHCT541-Q100

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

74HC365; 74HCT365. Hex buffer/line driver; 3-state

74HC153-Q100; 74HCT153-Q100

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

74HC08-Q100; 74HCT08-Q100

74LVC07A-Q100. Hex buffer with open-drain outputs

Triple inverting Schmitt trigger

Transcription:

Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (noe). LOW at noe causes the output to assume a high-impedance OFF-state. The HC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-114E: exceeds 2000 V MM JESD22-115-: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C Table 1. Type number Ordering information Package Temperature range Name Description Version 74HC2G126DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 74HCT2G126DP 74HC2G126DC 40 C to +125 C VSSOP8 body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; SOT765-1 74HCT2G126DC 74HC2G126GD 40 C to +125 C XSON8U 8 leads; body width 2.3 mm plastic extremely thin small outline package; no SOT996-2 74HCT2G126GD leads; 8 terminals; UTLP based; body 3 2 0.5 mm

4. Marking Table 2. Marking codes Type number Marking [1] 74HC2G126DP 26 74HCT2G126DP C26 74HC2G126DC 26 74HCT2G126DC C26 74HC2G126GD 26 74HCT2G126GD C26 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 1 5 7 1 1OE 2 2OE 1Y 2Y mna946 6 3 2 1 5 7 EN1 1 mna947 6 3 n noe ny mna234 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 6. Pinning information 6.1 Pinning 74HC2G126 74HCT2G126 74HC2G126 74HCT2G126 1OE 1 1 2 8 7 V CC 2OE 1OE 1 8 V CC 2Y 3 6 1Y 1 2Y 2 3 7 6 2OE 1Y GND 4 5 2 GND 4 5 2 001aaj263 001aaj262 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8U) Product data sheet Rev. 04 27 pril 2009 2 of 15

6.2 Pin description Table 3. Pin description Symbol Pin Description 1OE, 2OE 1, 7 output enable input (active LOW) 1, 2 2, 5 data input GND 4 ground (0 V) 1Y, 2Y 6, 3 data output V CC 8 supply voltage 7. Functional description Table 4. Function table [1] Control Input Output noe n ny H L L H H H L X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V V I input voltage 0.5 +7.0 V I IK input clamping current V I < 0.5 V [1] 20 - m I OK output clamping current V O < 0.5 V or V O >V CC + 0.5 V [1] - ±20 m I O output current 0.5 V < V O <V CC + 0.5 V - ±25 m I CC supply current - 75 m I GND ground current 75 - m T stg storage temperature 65 +150 C P tot total power dissipation T amb = 40 C to +125 C [2] - 250 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P tot derates linearly with 2.5 mw/k. For VSSOP8 package: above 110 C the value of P tot derates linearly with 8 mw/k. For XSON8U package: above 118 C the value of P tot derates linearly with 7.8 mw/k. Product data sheet Rev. 04 27 pril 2009 3 of 15

9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC2G126 74HCT2G126 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V V I input voltage 0-5.5 0-5.5 V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +125 40 +25 +125 C t/ V input transition rise V CC = 3.3 V ± 0.3 V - - 100 - - - ns/v and fall rate V CC = 5.0 V ± 0.5 V - - 20 - - 20 ns/v 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit 74HC2G126 V IH HIGH-level input voltage V IL V OH V OL I OZ I I LOW-level input voltage HIGH-level output voltage LOW-level output voltage OFF-state output current input leakage current Min Typ Max Min Max Min Max V CC = 2.0 V 1.5 - - 1.5-1.5 - V V CC = 3.0 V 2.1 - - 2.1-2.1 - V V CC = 5.5 V 3.85 - - 3.85-3.85 - V V CC = 2.0 V - - 0.5-0.5-0.5 V V CC = 3.0 V - - 0.9-0.9-0.9 V V CC = 5.5 V - - 1.65-1.65-1.65 V V I = V IH or V IL I O = 50 µ; V CC = 2.0 V 1.9 2.0-1.9-1.9 - V I O = 50 µ; V CC = 3.0 V 2.9 3.0-2.9-2.9 - V I O = 50 µ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 4.0 m; V CC = 3.0 V 2.58 - - 2.48-2.40 - V I O = 8.0 m; V CC = 4.5 V 3.94 - - 3.8-3.70 - V V I = V IH or V IL I O = 50 µ; V CC = 2.0 V - 0 0.1-0.1-0.1 V I O = 50 µ; V CC = 3.0 V - 0 0.1-0.1-0.1 V I O = 50 µ; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 4.0 m; V CC = 3.0 V - - 0.36-0.44-0.55 V I O = 8.0 m; V CC = 4.5 V - - 0.36-0.44-0.55 V V I =V CC or GND; V CC = 5.5 V V I = 5.5 V or GND; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V - - 0.25-2.5-10 µ - - 0.1-1.0-2.0 µ - - 1.0-10 - 40 µ Product data sheet Rev. 04 27 pril 2009 4 of 15

Table 7. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit C I input capacitance 74HCT2G126 V IH HIGH-level input voltage V IL LOW-level input voltage V OH HIGH-level output voltage V OL I OZ I I LOW-level output voltage OFF-state output current input leakage current 11. Dynamic characteristics - 1.5 10-10 - 10 pf V CC = 4.5 V to 5.5 V 2.0 - - 2.0-2.0 - V V CC = 4.5 V to 5.5 V - - 0.8-0.8-0.8 V V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ 4.4 4.5-4.4-4.4 - V I O = 8.0 m 3.94 - - 3.8-3.70 - V V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ - 0 0.1-0.1-0.1 V I O = 8.0 m - - 0.36-0.44-0.55 V V I =V CC or GND; V CC = 5.5 V V I = 5.5 V or GND; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V I CC C I additional supply current input capacitance per input pin; V I = 3.4 V; other inputs at V CC or GND; I O = 0 ; V CC = 5.5 V Min Typ Max Min Max Min Max - - 0.25-2.5-10 µ - - 0.1-1.0-2.0 µ - - 1.0-10 - 40 µ - - 1.35-1.5-1.5 m - 1.5 10-10 - 10 pf Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit 74HC2G126 t pd propagation delay n to ny; see Figure 6 [1] V CC = 3.0 V to 3.6 V [2] Min Typ Max Min Max Min Max C L = 15 pf - 4.7 8.0 1.0 9.5 1.0 11.5 ns C L = 50 pf - 6.6 11.5 1.0 13.0 1.0 14.5 ns V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 3.4 5.5 1.0 6.5 1.0 7.0 ns C L = 50 pf - 4.8 7.5 1.0 8.5 1.0 9.5 ns Product data sheet Rev. 04 27 pril 2009 5 of 15

Table 8. Dynamic characteristics continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max t en enable time noe to ny; see Figure 7 [1] V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 5.0 8.0 1.0 9.5 1.0 11.5 ns C L = 50 pf - 6.9 11.5 1.0 13.0 1.0 14.5 ns V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 3.6 5.1 1.0 6.0 1.0 6.5 ns C L = 50 pf - 4.9 7.5 1.0 9.0 1.0 9.5 ns t dis disable time noe to ny; see Figure 7 [1] V CC = 3.0 V to 3.6 V [2] C L = 15 pf - 6.0 9.7 1.0 11.5 1.0 12.5 ns C L = 50 pf - 8.3 13.2 1.0 15.0 1.0 16.5 ns V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 4.1 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 5.7 8.8 1.0 10.0 1.0 11.0 ns C PD power dissipation capacitance per buffer; C L = 50 pf; f i = 1 MHz; V I = GND to V CC [4] - 10 - - - - - pf 74HCT2G126 t pd propagation delay n to ny; see Figure 6 [1] V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 3.4 5.5 1.0 6.5 1.0 7.0 ns C L = 50 pf - 4.8 7.5 1.0 8.5 1.0 9.5 ns t en enable time noe to ny; see Figure 7 [1] V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 3.9 5.1 1.0 6.0 1.0 6.5 ns C L = 50 pf - 5.1 7.5 1.0 9.0 1.0 9.5 ns t dis disable time noe to ny; see Figure 7 [1] V CC = 4.5 V to 5.5 V [3] C L = 15 pf - 4.5 6.8 1.0 8.0 1.0 8.5 ns C L = 50 pf - 6.1 8.8 1.0 10.0 1.0 11.0 ns Product data sheet Rev. 04 27 pril 2009 6 of 15

Table 8. Dynamic characteristics continued GND = 0 V; for test circuit see Figure 8. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max [4] - 10 - - - - - pf C PD power dissipation capacitance per buffer; C L = 50 pf; f i = 1 MHz; V I = GND to V CC [1] t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. [2] Typical values are measured at V CC = 3.3 V. [3] Typical values are measured at V CC = 5.0 V. [4] C PD is used to determine the dynamic power dissipation P D (µw). P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts. 12. Waveforms V I n input GND t PHL t PLH V OH ny output V OL mna230 Fig 6. Measurement points are given in Table 9. Logic levels: V OL and V OH are typical output voltage levels that occur with the output load. Input (n) to output (ny) propagation delays Product data sheet Rev. 04 27 pril 2009 7 of 15

V I noe input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled outputs enabled mna949 Fig 7. Measurement points are given in Table 9. Logic levels: V OL and V OH are typical output voltage levels that occur with the output load. Enable and disable times Table 9. Measurement points Type Input Output V X V Y 74HC2G126 0.5V CC 0.5V CC V OL + 0.3 V V OH 0.3 V 74HCT2G126 1.5 V 0.5V CC V OL + 0.3 V V OH 0.3 V Product data sheet Rev. 04 27 pril 2009 8 of 15

V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC G VI DUT VO RL S1 open RT CL 001aad983 Fig 8. Test data is given in Table 10. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Test circuit for measuring switching times Table 10. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC2G126 V CC 3 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT2G126 3 V 3 ns 15 pf, 50 pf 1 kω open GND V CC Product data sheet Rev. 04 27 pril 2009 9 of 15

13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E X c y H E v M Z 8 5 2 1 ( 3 ) pin 1 index L p θ L 1 4 detail X e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1.1 0.15 0.00 2 3 b p c D (1) E (1) e H E L L p v w y Z (1) θ 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT505-2 - - - 02-01-16 Fig 9. Package outline SOT505-2 (TSSOP8) Product data sheet Rev. 04 27 pril 2009 10 of 15

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E X c y H E v M Z 8 5 Q 2 1 pin 1 index ( 3 ) L p θ 1 4 detail X L e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1 0.15 0.00 2 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8 0 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT765-1 MO-187 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) Product data sheet Rev. 04 27 pril 2009 11 of 15

XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B E 1 detail X terminal 1 index area L 1 e 1 e b 1 4 v M w M C C B y 1 C C y L 2 L 8 5 X DIMENSIONS (mm are the original dimensions) UNIT max mm 0.5 1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E e e 1 L L 1 3.1 2.9 0.5 1.5 0 1 2 mm scale 0.5 0.3 0.15 0.05 L 2 v w 0.6 0.4 0.1 0.05 0.05 y y 1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT996-2 - - - - - - EUROPEN PROJECTION ISSUE DTE 07-12-18 07-12-21 Fig 11. Package outline SOT996-2 (XSON8U) Product data sheet Rev. 04 27 pril 2009 12 of 15

14. bbreviations Table 11. cronym CMOS CDM DUT ESD HBM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change Supersedes notice 20090427 Product data sheet - 74HC_HCT2G126_3 Modifications: Table 5: the total power dissipation value for XSON8U has been changed. 74HC_HCT2G126_3 20090115 Product data sheet - 74HC_HCT2G126_2 74HC_HCT2G126_2 20040921 Product data sheet - 74HC_HCT2G126_1 74HC_HCT2G126_1 20040113 Product specification - - Product data sheet Rev. 04 27 pril 2009 13 of 15

16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Product data sheet Rev. 04 27 pril 2009 14 of 15

18. Contents 1 General description...................... 1 2 Features............................... 1 3 Ordering information..................... 1 4 Marking................................ 2 5 Functional diagram...................... 2 6 Pinning information...................... 2 6.1 Pinning............................... 2 6.2 Pin description......................... 3 7 Functional description................... 3 8 Limiting values.......................... 3 9 Recommended operating conditions........ 4 10 Static characteristics..................... 4 11 Dynamic characteristics.................. 5 12 Waveforms............................. 7 13 Package outline........................ 10 14 bbreviations.......................... 13 15 Revision history........................ 13 16 Legal information....................... 14 16.1 Data sheet status...................... 14 16.2 Definitions............................ 14 16.3 Disclaimers........................... 14 16.4 Trademarks........................... 14 17 Contact information..................... 14 18 Contents.............................. 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 pril 2009 Document identifier: