Analysis and Desin of Analo Interated Circuits ecture 7 Differential Amplifiers Michael H. Perrott February 1, 01 Copyriht 01 by Michael H. Perrott All rihts reserved.
Review Proposed Thevenin CMOS Transistor Model Hybrid-π Model R thd R D Key Small-Sinal Parameters R G d Parameter Stron Inversion Weak Inversion R th v s m v s - mb v s r o m μ n C ox (W/)I D qi D nkt s mb γ m Φ F + V SB (n-1)qi D nkt R ths v s R S Note: mb = 0 if R S =0 or V sb =0 r o 1 λi D 1 λi D Thevenin Resistances R G R th I D d s R D Rthd R ths R S Exact R thd = r o (1+( m + mb )R S )+R S R th = infinite R ths = 1+R D /r o Approximation ( mb << m, m r o >> 1) R thd = r o (1+ m R S ) R th = infinite R ths = 1 + R D /r o m r o 1 m + mb ( )( ) 1 m Proposed Small Sinal Transistor Model R th v R ths A v v i s αi s Rthd s Exact Approximation A v = m r m o A v = 1 ( m + mb << m, m r o >>1) mb (R D << r ) o α = 1+R D /R thd α = 1 (R D <<R thd ) d
Key Observations Thevenin Resistances R G R th I D d s R D Rthd R ths R S Exact R thd = r o (1+( m + mb )R S )+R S R th = infinite R ths = 1+R D /r o Approximation ( mb << m, m r o >> 1) R thd = r o (1+ m R S ) R th = infinite R ths = 1 + R D /r o m 1 m + mb ( )( ) r o 1 m Proposed Small Sinal Transistor Model R th v R ths A v v i s αi s Rthd s Exact Approximation A v = m r m o A v = 1 ( m + mb << m, m r o >>1) mb (R D << r ) o α = 1+R D /R thd α = 1 (R D <<R thd ) d For calculations focusin on sinal flow from ate or source to the drain - Observe that current throuh R d equals i s True since * R thd /(R d + R thd ) = 1 You can avoid doin calculations involvin or R thd For calculations focusin on sinal flow from the drain - Drain simply looks like impedance R thd 3
Basic Sinle-Stae Amplifiers and Current Mirrors Common Source Common Gate Source Follower Z V out Z V out Source V in Vout Source V in i d i d i in Z Common Source with Source Deeneration Source Z i d V out Current Mirror Source V in i in i out Z S W M 4
Today We Will ook At Differential Amplifiers Common Source Common Gate Source Follower Z V out Z V out Source V in Vout Source V in i d i d i in Z Common Source with Source Deeneration Source Differential Amplifier Z Source V in i d V out Current Mirror i in i out Z Z V in- Z S W M I bias 5
Differential and Common Mode Sinals -V d / V d / V c Consider positive and neative input terminal sinals V i+ and V i - Define differential sinal as: Define common mode sinal as: V id = V + in V in V ic =(V + in + V We can create arbitrary V i+ and V i- sinals from differential and common mode components: in )/ V + in = V ic + 1 V id V in = V ic 1 V id This also applies to differential output sinals: V + o = V oc + 1 V od V o = V oc 1 V od 6
Differential Amplifier I bias1 V in- M 3 M 4 Useful for amplifyin sinals in the presence of noise - Common-mode noise is rejected Useful for hih speed diital circuits - ow voltae swin allows faster ate/buffer performance 7
First Steps in Small Sinal Modelin I bias1 V in- V in- M 3 M 4 R thd4 = r o4 Small sinal analysis assumes linearity - Impact of M 4 on amplifier is to simply present its drain impedance to the diff pair transistors ( and M ) - Impact of and V in- can be evaluated separately and then added (i.e., superposition) By symmetry, we need only determine impact of Calculation of V in- impact directly follows 8
Calculate Impact of usin Thevenin Models r o4 M i s1 R ths1 R th1 v 1 A v1 v 1 α 1 i s1 R thd1 α R ths i s R thd i s General Model r o4 Common Gate Analysis follows fairly easily, but there is a simpler way! 9
Method of Differential Amplifier Analysis V in- V id -V id r o4 V ic r o4 Partition input sinals into common-mode and differential components By superposition, we can add the results to determine the overall impact of the input sinals 10
Differential Analysis V id -V id i s1 = i s i R = 0 R 1 R V id -V id R 1 R V id -V id i s1 i s i R r o4 Key observations - Inputs are equal in manitude but opposite in sin to each other - By linearity and symmetry, i s1 must equal -i s This implies i R is zero, so that voltae drop across r o4 is zero The sources of and M are therefore at incremental round and decoupled from each other! Analysis can now be done on identical half-circuits What is the differential DC ain? 11
Common Mode Analysis i s1 = i s i R = i s1 = i s V ic V ic V ic V ic V ic V ic i s1 ir i s i s1 i diff = 0 i s r o4 r o4 r o4 r o4 r o4 Key observations - Inputs are equal to each other - By linearity and symmetry, i s1 must equal i s This implies i R = i s1 = i s - We can view r o4 as two parallel resistors that have equal current runnin throuh them Analysis can also be done on two identical half-circuits What is the common mode DC ain? 1
Useful Metric for Differential Amplifiers: CMRR V input V noise V id =V si V od Common Mode Rejection Ratio (CMRR) - Define: a vd : differential ain, a vc : common mode ain CMRR = µ avd a vc - CMRR corresponds to ratio of differential to common mode ain and is related to received sinal-to-noise ratio V od = a vd V si + a vc V noise Sinal µ µ Noise = avd Vsi =CMRR a vc V noise µ Vsi V noise 13
Another Useful Metric for Differential Amplifiers: PSRR V sup + V input V noise V id =V si V od Power Supply Rejection Ratio (PSRR) - a vd : differential ain - a vp+ : positive power supply ain - a vp- : neative power supply ain PSRR + = µ avd a vp+ PSRR = V sup - µ avd a vp 14
Example: Calculate CMRR and PSRR V in- V id -V id r o4 V ic r o4 First determine a vd, a vc, a vp+, and a vp- Then calculate CMRR and PSRR - Note that CMRR and PSRR are often expressed in db Example: CMRR = 0lo(a vd /a vc ) 15
Common Mode Voltae Rane of Differential Amplifier Id1 I d I bias ΔV 1 ΔV V in- V TH +ΔV 1 I ss V TH +ΔV ΔV 4 M 3 M 4 While keepin all devices in saturation: - What is the maximum common mode output rane? Assume V id = 0 - What is the maximum common mode input rane? Assume V od = 0 16
are Sinal Behavior of Differential Mode Operation V id = -V in- = (V TH +ΔV 1 ) - (V TH +ΔV ) = ΔV 1 -ΔV I d1 I d V id = I d1 k I d k where k = μ n C ox W I bias V in- V id = I ss +I od / k I ss -I od / k where I od = I d1 -I d V TH +ΔV 1 V TH +ΔV square and solve for I od M 3 I ss M 4 I ss I od = KV id for V k id < I ss k -V id I od = I d1 -I d I ss I ss k I ss k V id = -V in- -I ss Note: above analysis assumes stron inversion 17