CONSTANT CURRENT STRESS OF ULTRATHIN GATE DIELECTRICS Y. Sun School of Electrical & Electronic Engineering Nayang Technological University Nanyang Avenue, Singapore 639798 e-mail: 14794258@ntu.edu.sg Keywords: nmosfet, reliability, soft breakdown, hard breakdown, constant current stress. Abstract Constant current stresses at 1 o C are performed in nmosfets with 2Å gate oxide with areas of.3 x.15 µm 2,.3 x.3 µm 2, and.2 x.15 µm 2. Electrical characteristics of dielectric breakdown are studied by various measurements, including the voltage time characteristics monitored during the stress, the pre- and post breakdown I ds V ds curves, and the pre- and post breakdown I g V g curves. Unlike in most of the researches done so far where large area MOS capacitors are stressed, nmosfets with ultra thin gate oxide of small area are used in this project. 1 Introduction It has been reported that soft breakdown (SBD) dominates for gate oxide layers thinner than 5nm during constant current or constant voltage stress of MOSFET devices [1]. Although the exact physical mechanism responsible for the intrinsic dielectric breakdown is still an open question, it is widely accepted that, when stressed by an applied current or voltage, the gate oxide layer loses its insulating properties in two stages. First, in the wearout phase, traps are created within the oxide and at the Si/SiO 2 interface, leading to an increase of the leakage current through the gate oxide. Several physical models have been proposed to explain defect generation and the wearout phase of oxide degradation, such as thermochemical model [7], anode hole injection (AHI) model [3, 4, 5], and anode hydrogen release (AHR) model [6], etc. As the defects accumulate with time and eventually reach a critical density, the second stage, the breakdown event, is triggered by the completion of a percolation path linking anode and cathode. Parameters that affect when and how the dielectric breakdown occurs include the applied stress current density (or voltage), temperature, dielectric thickness, device dielectric area, and intrinsic dielectric lifetime. Alam et al. [8] claimed that it is the power dissipation, not the stored energy, which determines the severity of oxide breakdown, whether it is soft or hard. For accurate reliability projections, a correct methodology must be applied in the accelerated tests. Generally there are two distinct stress methods, namely constant voltage stress (CVS) and constant current stress (CCS). While most of the researches so far are concentrated on CVS, few results from CCS can be found in literature. The author believe that the accurate projection of dielectric lifetime must be performed with an eye to the actual circuit conditions which may stress the oxides in some combination of CVS and CCS. Thus, it is important to study the reliability of ultrathin gate dielectric intensively by CCS. In this paper, the current-voltage characteristics of MOSFET devices with a 2Å gate oxide are investigated by CCS. In Section 2, the experimental procedure is described. The results are presented and discussed in Section 3. Finally, conclusions are drawn in Section 4. 2 Experimental The samples used in the experiments were fabricated by a standard.15µm CMOS process. Each set of devices consist of three nmosfets of 2Å gate oxide layer, with device areas of.3 x.15 µm 2,.3 x.3 µm 2, and.2 x.15 µm 2. Constant current stresses at 1 o C in nmosfets were performed through the following steps. 1) At the beginning, the current-voltage characteristic of the transistor was measured to ensure that the device was working properly before stressing test. 2) The transistor was stressed with the source, drain and substrate tied to the ground and with a constant current injected to the gate electrode. The voltagetime characteristics during the constant current stress were monitored by an Agilent Technologies 4156C Semiconductor parameter analyzer. 3) Then, the transistor characteristics after the breakdown were measured to compare with prebreakdown characteristics. 4) Steps 1-3 were repeated in one set of transistors by applying the same current density. The above procedures were repeated by applying different current densities for comparison. 3 Results and discussion
3.1 Breakdown characteristics Figure 1 shows the breakdown behaviour in a 2 Å gate oxide with device area of.3 x.3 µm 2 after CCS at 12nA (i.e. current density = 1.33 µa/µm 2 ). The breakdown characteristic shows staircase decrease in voltage culminating in the hard breakdown (HBD). The voltage drop in steps during the breakdown process is the consequence of the SBD events since it is a highly localized failure with a slight decrease in the gate voltage. HBD is observed as a sudden collapse in the gate voltage. However, for the same device, HBD is not observed within the same stress time for stress current lower than 1nA. It is noticed that the time to breakdown is too short in this case, within merely 2 second. It is probably due to the current density of 1.33 µa/µm 2, which is quite large for CCS in such a small area nmosfet with only 2Å gate oxide Gate Voltage (V) 5 4 3 2 1 1 2 3 4 Figure 1: Voltage - time characteristic during the constant current stress at 12nA. Area =.3 x.3 µm2. It is observed that SBD is always accompanied by noise or voltage fluctuations, as shown in Figure 2. There were several explanations for the fluctuations behaviour of soft breakdown in literature. In the study done by Depas et al. [2], the noise was explained as multiple tunneling events through electron traps after breakdown is triggered by the critical density of traps. Lee et al. [1] demonstrated that a localized damage was formed in the oxide leading to a thinner oxide. The fluctuation was the result of dynamic trapping and detrapping. The corresponding drain, source and substrate currents are also monitored during the stress as shown in Figure 3, 4 and 5. It is observed that the drain and source currents have a concurrent jump along with the gate voltage. The location of SBD in the gate oxide can be roughly determined by observing all the currents at the terminals of the nmosfet. It is found that the drain current has a notable increase in magnitude while both the source and substrate current have a decrease in magnitude (Id + Is + Isub = Ig = constant for CCS). Therefore, it is postulated that the SBD occurred nearer to the drain side. Gate Voltage (V) 4.5 4 3.5 3 2.5 2 1.5 1.5 Figure 2: Breakdown behavior during constant current stress at 1nA. Area =.3 x.3 µm2. Drain Current Id (A) -2.5E-8-3.E-8-3.5E-8-4.E-8-4.5E-8-5.E-8-5.5E-8 Figure 3: Monitored drain current of the same sample stressed at 1nA till SBD. Source Current Is (A) -4.E-8-4.5E-8-5.E-8-5.5E-8-6.E-8 Figure 4: Monitored source current of the same sample. Substrate Current Isub (A) 2.E-8 1.E-8.E+ -1.E-8-2.E-8-3.E-8-4.E-8 Figure 5: Monitored substrate current for the same sample.
3.2 Post breakdown transistor characteristics During constant current stresses, several breakdown events can be induced in each single sample. After the first breakdown event, the stress is stopped to measure the I ds -V ds characteristic. This is carried out at low voltages to avoid opening new breakdown path during the measurement. The pre- and post breakdown I ds -V ds characteristics of the same sample in Figure 2 are compared in Figure 6. The first breakdown event is shown to be SBD since the transistor characteristic of the sample does not altered. The post breakdown I ds -V ds curve is shifted down by a small value, indicating that the current drivability of the transistor is degraded although not significantly after the SBD. 1.E-4 8.E-5 6.E-5 4.E-5 2.E-5.E+ Pre-SBD Post SBD.5 1 1.5 Figure 6: Comparison of pre- and post soft breakdown I ds -V ds characteristic for.3 x.3 µm 2 nmosfet stressed with a constant current at 1nA. Current density = 1.11 µa/µm 2. In another experiment, a.3 x.15 µm 2 nmosfet was stressed at a current density of 6.67 µa/µm 2, which is six times larger. The first breakdown event is manifested as HBD. It is found that the post breakdown I ds -V ds characteristic is pure ohmic (See Fig. 7). This is because the insulating property of the gate oxide is totally lost after HBD and the transistor functions like a resistor..4.3.2.1 -.1 -.2 -.3.5 1 Figure 7: Post hard breakdown I ds -V ds characteristic for.3 x.15 µm 2 nmosfet stressed with a constant current at 3nA. Current density = 6.67 µa/µm 2. 1.5 Another type of post breakdown I ds -V ds characteristic is also observed. Figure 8 shows the I ds -V ds characteristic after the final HBD illustrated in Figure 1. The I ds -V ds curve shows the catastrophic failure of the device after the breakdown since the transistor characteristic has been altered. The severe device degradation is probably due to the high power dissipation, and thus severe thermal damage during the breakdown. The current voltage characteristic after breakdown is not pure ohmic suggesting that the HBD is not as severe as the case shown in Figure 7. 1.E-4 5.E-5.E+ -5.E-5-1.E-4-1.5E-4-2.E-4.5 1 1.5 Figure 8: Post breakdown I ds -V ds characteristic for.3 x.3 µm 2 nmosfet stressed with a constant current at 12nA. Current density = 1.33 µa/µm 2. 3.3 Post breakdown gate leakage The severity of breakdown can also be determined by monitoring the pre- and post breakdown I g V g characteristics. The gate leakage currents I g of the three nmosfet with different areas and stressed under the same current density of.7 µa/µm 2 are shown (open shapes) in Figure 9 as a function of the applied gate voltage V g. These curved were taken after stressing the nmosfet with a constant current density until the first breakdown event was detected. Due to a much lower current density applied, the first event is observed as SBD in all the three nmosfet. The I g V g curve of a fresh nmosfet (filled square) is also plotted for comparison. It is observed that the gate current increases by only about one to two orders of magnitude after the occurrence of SBD in the voltage range applied. It has been shown that the post soft breakdown I-V characteristic has a weak dependence on the area provided the same current density is applied. The gate leakage characteristics of the nmosfet with 2Å gate oxide after the HBD occurred are also shown in Figure 9. The bold line corresponds to the post hard breakdown I g V g curve of.3 x.15 µm 2 nmosfet stressed with a constant current density of 6.67 µa/µm 2, while the thin line shows the I g V g curve of.3 x.3 µm 2 nmosfet stressed with a constant current density of 1.33 µa/µm 2 after the final HBD occurred. It is found that the HBD for the first case is much severer, as a larger increase of gate leakage current is observed. This verifies the results obtained in Section 3.2,
where the post breakdown I ds -V ds curve is pure ohmic for the first case. Gate Current Ig (A) 1.E-2 1.E-4 1.E-6 1.E-8 1.E-1 1.E-12 1.E-14-1.5-1 -.5.5 1 1.5 Gate Voltage Vg (V) Figure 9: Pre- and post breakdown I g V g curves of nmosfet with a 2Å gate oxide with different areas..3x.15 µm 2, J=6.67 µa/µm 2.3x.3 µm 2, J=1.33 µa/µm 2.3x.15 µm 2, J=.7 µa/µm 2.3x.3 µm 2, J=.7 µa/µm 2.2x.15 µm 2, J=.7 µa/µm 2.2x.15 µm 2, Fresh 1) the current drivability of the transistor is slightly degraded while the typical transistor characteristic still remains. 2) the leakage current through the gate oxide increases by about one to two orders of magnitude. 3) post breakdown I V characteristic has a weak dependence on the area. After hard breakdown occurs in ultrathin gate oxide, 1) the transistor characteristic either shows ohmic in nature or severe thermal damage depending on the stress condition and device geometry. 2) post breakdown I g V g characteristic shows ohmic conduction with a smooth curve and a significantly large increase in gate leakage current, by more than four orders of magnitude. The analysis in this report is limited by the relatively small sample size employed. In the future, further study on reliability statistics shall be performed on large sample size and various sample geometries. Moreover, the reliability of high-k dielectric, for instance silicon nitride, shall be investigated. Acknowledgements The author would like to thank Assoc. Prof. Pey Kin Leong for intriguing discussion and kind help in various aspects of this project, Mr. Tung Chih-Hang and Mr. Tang Lei Jun for their help on the experiments in Institute of Microelectronics. 4 Conclusion Unlike in most of the researches done so far where large area MOS capacitors are used in the stress tests, in this project, CCS at 1 o C was performed in nmosfets with 2Å gate oxide with areas of.3 x.15 µm 2,.3 x.3 µm 2, and.2 x.15 µm 2. Electrical characteristics of breakdown was studied by various measurements, including the voltage time characteristics monitored during the stress, the pre- and post breakdown I ds V ds curves and the pre- and post breakdown I g V g curves. From the monitored voltage time characteristic, SBD is observed as a slight voltage drop accompanied by voltage fluctuations or noise. HBD, on the contrary, is observed as a sudden collapse in the gate voltage. Several soft and hard breakdown events can occur on the same sample, which is evident by the staircase like decrease in gate voltage. Moreover, by monitoring all the terminal currents of the nmosfet during the stress, the location of SBD in the gate oxide can be roughly determined. References [1] S. H. Lee, B. J. Cho, J. C. Jim, and S. H. Choi, Quasibreakdown of ultrathin gate oxide under high field stress, IEDM Tech. Dig., pp.65-68, (1994). [2] M. Depas, T. Nigam and M.H. Heyns, Soft breakdown of ultra-thin gate oxide layers, IEEE Trans. Electron Devices, vol.43, pp. 1499-153, (1996). [3] K. F. Schuegraf et al., Hole injection in SiO2 breakdown model for very low voltage lifetime extrapolation, IEEE Trans. Electron Devices, vol. 41, pp. 761-766, (1994). [4] J. Bude, B. Weir, and P. Silverman, Explanation of stress induced damage in thin oxides, IEDM Tech. Dig., pp. 179-181, (1998). [5] M. Alam, J. Bude, and A. Ghetti, Field acceleration for oxide break-down-can an accurate anode hole injection model resolve the E versus 1/E controversy, Proc. 38 th IRPS, pp. 21-26, (2). From the study of the I ds V ds and the gate leakage characteristics, the following conclusion can be drawn. [6] D. J. DiMaria and J. W. Stasiak, Trap creation in After soft breakdown occurs in ultrathin gate oxide, silicon dioxide produced by hot electrons, J. Appl. Phys., vol.65, pp. 2343-2355, (1989).
[7] J. W. McPherson and H. C. Mogul, Underlying physics of the thermochemical E model in describing low field time dependent dielectric breakdown in SiO2 thin films, J. Appl. Phys., vol. 84, pp. 1513-1523, (1998). [8] M. A. Alam, B. E. Weir, and P. J. Silverman, A study of soft and hard breakdown Part II: Principle of area, thickness, and voltage scaling, IEEE Trans. Electron Devices, vol. 49, pp. 239-246, (Feb. 22).