L4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES

Similar documents
Unit 2 Session - 6 Combinational Logic Circuits

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

This form sometimes used in logic circuit, example:

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

CprE 281: Digital Logic

Chapter 4 Optimized Implementation of Logic Functions

Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011

Karnaugh Maps Objectives

ELCT201: DIGITAL LOGIC DESIGN

Combinational Logic. Review of Combinational Logic 1

Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...

CPE100: Digital Logic Design I

UNIT 5 KARNAUGH MAPS Spring 2011

Combinatorial Logic Design Principles

Gate-Level Minimization

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Simplifying Logic Circuits with Karnaugh Maps

Digital Logic Design. Combinational Logic

211: Computer Architecture Summer 2016

Logical Design of Digital Systems

Karnaugh Map & Boolean Expression Simplification

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Chapter 7 Logic Circuits

Optimizations and Tradeoffs. Combinational Logic Optimization

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

MODULAR CIRCUITS CHAPTER 7

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

MC9211 Computer Organization

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

CSE 140 Midterm I - Solution

CHAPTER III BOOLEAN ALGEBRA

EEE130 Digital Electronics I Lecture #4

Chapter 2 Combinational Logic Circuits

Digital Circuit And Logic Design I. Lecture 4

CHAPTER 5 KARNAUGH MAPS

14:332:231 DIGITAL LOGIC DESIGN

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Week-I. Combinational Logic & Circuits

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

Karnaugh Maps (K-Maps)

Chapter 2. Boolean Algebra and Logic Gates

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

CHAPTER III BOOLEAN ALGEBRA

CSE 140: Components and Design Techniques for Digital Systems

Chapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms

Boolean Algebra and Logic Simplification

CHAPTER 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev

Review for Test 1 : Ch1 5

Logic Design. Chapter 2: Introduction to Logic Circuits

L2: Combinational Logic Design (Construction and Boolean Algebra)

ECE 2300 Digital Logic & Computer Organization

Systems I: Computer Organization and Architecture

CHAPTER1: Digital Logic Circuits Combination Circuits

Lecture 2 Review on Digital Logic (Part 1)

Midterm1 Review. Jan 24 Armita

Unit 6. Quine-McClusky Method. Unit 6 1

Chap 2. Combinational Logic Circuits

Lecture 4: Four Input K-Maps

Midterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes

Standard Expression Forms

DIGITAL ELECTRONICS & it0203 Semester 3

WEEK 3.1 MORE ON KARNAUGH MAPS

ENG2410 Digital Design Combinational Logic Circuits

Computer Science Final Examination Friday December 14 th 2001

Lecture (02) NAND and NOR Gates

E&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates

for Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Logic Design (Class 2.2 1/24/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE

ELC224C. Karnaugh Maps

CS 226: Digital Logic Design

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

EECS Variable Logic Functions

II. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):

ENGR 303 Introduction to Logic Design Lecture 3. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

2009 Spring CS211 Digital Systems & Lab CHAPTER 2: INTRODUCTION TO LOGIC CIRCUITS

DO NOT COPY DO NOT COPY

Logic Design I (17.341) Fall Lecture Outline

Administrative Notes. Chapter 2 <9>

Chapter 2 Combinational logic

Chapter 2: Princess Sumaya Univ. Computer Engineering Dept.

Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Binary logic consists of binary variables and logical operations. The variables are

Motivation. CS/EE 3700 : Fundamentals of Digital System Design

Lecture 7: Karnaugh Map, Don t Cares

Chapter 2. Digital Logic Basics

14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis

Chapter 4: Designing Combinational Systems Uchechukwu Ofoegbu

Boolean Algebra and logic gates

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

Number System conversions

Minimization techniques

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Boolean Algebra and Logic Gates

Chapter 2: Boolean Algebra and Logic Gates

Transcription:

L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se

Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore ONLY on the PRESENT value of the input signal Lecture 4 - Lecture 7 IE204 Digital Design, Autumn 204 2

Sequential system a(t) f(a(t)) A sequential system has a built-in memory - its output depends therefore BOTH on the PRESENT and PREVIOUS value(s) of the input signal Lecture 8 - Lecture 3 IE204 Digital Design, Autumn 204 3

BV pp. 68-2 This lecture covers IE204 Digital Design, HT 20 4

Minimization of Boolean expressions Example: Minterms of the function are m(,2,3) or f = x x 0 + x x 0 + x x 0 Using Boolean algebra, we can shorten the expression to: f = x x 0 + x x 0 + x x 0 = x x 0 + x (x 0 + x 0 ) = x x 0 + x () = x x 0 + x ( + x 0 ) = = x x 0 + x + x x 0 = x 0 (x + x ) + x = x 0 () + x = x + x 0 IE204 Digital Design, Autumn 204 4

Minterms A minterm MUST contain all variables, otherwise it is not a minterm A minterm represents the combination of values of function's valiables for which the function evaluates to f = Sm(0,2,3) = x x 3 +x x 3 +x x 3 IE204 Digital Design, Autumn 204 5

Maxterms A maxterm MUST contain all variables, otherwise it is not a maxterm A minterm represents the combination of values of function's valiables for which the function evaluates to 0 f = PM (0,2,3) = (x + +x 3 ) (x + +x 3 ) (x + +x 3 ) IE204 Digital Design, Autumn 204 6

Commonly used functions in twodimensional table-form x 0 x 0 x 0 x 0 0 0 0 0 0 x 0 x 0 0 0 0 0 0 x 0 x 0 0 AND OR XOR 0 x 0 x 0 0 0 0 NAND NOR XNOR 0 x 0 x 0 0 0 x 0 0 0 NOT IE204 Digital Design, Autumn 204 7

3-dimensional Boolean space Size: abc 00 0 0 0-dimensional subspace -dimensional subspace b c a 00 0 0 0 00 0 2-dimensional subspace IE204 Digital Design, Autumn 204 8

Karnaugh map 0 00 0 Differ in the value of only one variable b = b c b = 0 00 0 bc a 00 0 0 a 000 00 0 IE204 Digital Design, Autumn 204 9

Minimizing 0 00 0 f(a,b,c) = Σm (0,2,3,5,7) b c 00 0 a 0 bc 00 0 0 a 000 00 IE204 Digital Design, Autumn 204 0

Implicants 0 00 0 Circle the minterms located "next to each other b c a 00 0 a 00 0 0 000 00 0 bc f (a,b,c) = Σm (0,2,3,5,7) IE204 Digital Design, Autumn 204

Literals and Product-Terms A given product-term in a sum-of-products form consists of several variables Each of the variables may appear complemented or non-complemented These variables are called literals f(a,b,c) = abc + ab + bc IE204 Digital Design, Autumn 204 2

Minterms and product-terms A minterm always contains all variables of a function A product-term may contain less variables Examples of minterms for three variable functions: abc, abc Examples of product-terms for three variable functions: abc, ab, a IE204 Digital Design, Autumn 204 3

Implicants and Covers Implicant - A product-term for which the function evaluates to Prime implicant - An implicant which is not contained in any other implicant A prime implicants cannot be expanded into a larger implicant Cover is a set of implicants which contains all minterms for which the function evaluates to IE204 Digital Design, Autumn 204 4

More implicant treminology A prime implicant is essential if there is a minterm covered by that implicant, but no other prime implicant Essential imlicants will always be included in a cover of a function If we can remove an implicant, but all minterms are still covered, then such an implicant is called redundant IE204 Digital Design, Autumn 204 5

Example 0 00 0 Redundant implicants - both are not necessary to cover the function b c 00 0 a 0 bc 00 0 0 a 000 00 f (a, b, c) = Σm (0,2,3,5,7) IE204 Digital Design, Autumn 204 6

Covers Minimum cover is a cover with the minimum number of cubes Prime cover is a cover consisting of only prime implicants Irredundant cover is a cover which does not contain any redundant implicants IE204 Digital Design, Autumn 204 7

Example Example: f (a, b, c, d) = abc + bd + cd is minimum, prime and irredundant cover for f ab cd 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 IE204 Digital Design, Autumn 204 8

Exact minimization Quine's Theorem: For any Boolean function, there exists a minimum cover which is prime Consequence: The search for a minimum cover can be restricted to covers with prime implicants only All minimum covers All prime covers IE204 Digital Design, Autumn 204 9

Two-level minimization IE204 Digital Design, Autumn 204 20

Minimum sum-of-product implementation b 0 ac 00 0 0 f = bc + ac + bc a b c f IE204 Digital Design, Autumn 204 2

Programmable Logic Array (PLA) Both AND and OR arrays are programmable x x 3 P OR plane P 2 P 3 P 4 AND plane f f 2 IE204 Digital Design, Autumn 204 22

Programmable Array Logic (PAL) Only the AND arrays are programmable x x 3 Which functions P, P 2, P 3 and P 4 represent? P P 2 P 3 f P 4 f 2 AND plane IE204 Digital Design, Autumn 204 23

Karnaugh map with 4 variables x x 0 x 3 00 0 0 00 0 0 We always circle an entire sub-space (as large as possible)!!! IE204 Digital Design, Autumn 204 24

Karnaugh map with 5 variables x 4 x x 0 x 3 000 00 0 00 0 0 00 00 0 x 3 x x 0 0 IE204 Digital Design, Autumn 204 25

Example x x 0 x 4 x 3 000 00 0 00 00 0 0 0 0 00 x 3 x x 0 IE204 Digital Design, Autumn 204 26

Karnaugh map with 6 variables x 4 x x 0 x 5 x 3 000 00 0 00 0 0 00 000 00 0 00 0 0 00 x 3 x x 0 IE204 Digital Design, Autumn 204 27

Example x x 0 x 5 x 4 x 3 000 00 0 00 0 0 00 000 00 0 00 0 0 00 x 3 x x 0 IE204 Digital Design, Autumn 204 28

Alternative: Circle 0s x 3 00 0 0 x x 0 00 0 0 0 x 3 00 0 0 x x 0 00 0 0 0 x 3 x x 0 = x 3 + +x +x 0 Circle the zeros is zeros is less than ones!!! IE204 Digital Design, Autumn 204 29

Incomplete functions with Often you can simplify a specification of the logic function knowing that some input combinations never occur For these combinations, we use the value "don t care" There are different symbols for "don't care" d', 'D', '-', 'ϕ', x' don t cares IE204 Digital Design, Autumn 204 30

Specification of incomplete functions x x 0 x x 0 x 3 00 0 0 x 3 00 0 0 00 0 0 0 00 0 0 0 0 0 0 0 x d d d d d d d d ( x + x 0 ) 0 0 0 0 x x 0 0 0 0 0 ( + x ) (A) SOP implementation (B) POS implementations Two implementations of the function f (x 3,..., x 0 ) = Sm(2, 4, 5, 6, 0) + D(2, 3, 4, 5). IE204 Digital Design, Autumn 204 3

Alternative notation x x 0 x x 0 x 3 00 0 0 x 3 00 0 0 00 0 0 0 00 0 0 0 0 0 0 0 x - - - - - - - - ( x + x 0 ) 0 0 0 0 x x 0 0 0 0 0 ( + x ) (A) SOP implementation (B) POS implementations Two implementations of the function f (x 3,..., x 0 ) = Sm(2, 4, 5, 6, 0) + D(2, 3, 4, 5). IE204 Digital Design, Autumn 204 32

Functions with multiple outputs x 3 00 0 0 x x 0 f 0 f 00 0 0 x x 0 x 3 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 f = f 0 +x 3 x 0 Different outputs can share implicants! IE204 Digital Design, Autumn 204 33

Multi-level minimization IE204 Digital Design, Autumn 204 34

Do we need multi-level logic? One can realize all the combinational circuits with two-level (AND-OR, OR-AND) The assumption is that all inputs are also availible in the inverted form (as in PAL, PLA) IE204 Digital Design, Autumn 204 35

Why multi-level logic? A multi-level implementation may have considerably less gates than a two-level implementation IE204 Digital Design, Autumn 204 36

Two strategies for multi-level logic. Factorisation 2. Functional Decomposition IE204 Digital Design, Autumn 204 37

Factorisation Suppose the following function is to be implemented f x x 3 x 4 x 5 x 6 x x 3 x 4 x 5 x 6 IE204 Digital Design, Autumn 204 38

Factorisation If we use the distributive law (L2, s.2, 2a), we can get the following multi-level implementation: f x x 3 x 4 x 5 x 6 x x 3 x 4 x 5 x 6 x x 4 x 6 ( x 3 x 5 x 3 x 5 ) IE204 Digital Design, Autumn 204 39

Factorization x x 3 x 4 x 6 x 5 x 3 x 5 f x x 4 x 6 ( x 3 x 5 x 3 x 5 ) IE204 Digital Design, Autumn 204 4

Functional decomposition One can often reduces the complexity of a logic function by reusing its sub-functions several times For implementation it means to share subcircuits in its construction IE204 Digital Design, Autumn 204 42

Functional Decomposition How can the following function implemented? f x x 3 x x 3 x x 4 x x 4 IE204 Digital Design, Autumn 204 43

Functional Decomposition Factorisation gives us f x x 3 x x 3 x x 4 x x 4 (x x )x 3 (x x )x 4 If we define a sub-function g as g x x x x 2 2 IE204 Digital Design, Autumn 204 44

So, we get Functional Decomposition where f gx 3 g x 4 g x x x x IE204 Digital Design, Autumn 204 45

Functional Decomposition Implementation x x 3 g f x 4 f gx 3 g x 4 x g g x x x x x 3 x 4 h f IE204 Digital Design, Autumn 204 46

Algorithms for minimization Karnaugh map minimization gives a good insight into how to minimize logic functions But to minimize the complex functions with the help of computer, there are better algorithms Chapter 4.9 and 4.0 in Brown/Vranesic provides an introduction to the minimization algorithms (for the interested student) IE204 Digital Design, Autumn 204 47

Summary Karnaugh maps are a good tool for minimizing logic functions with a few variables There are algorithms for both two-level and multi-level minimization Next lecture: BV pp. 250-280 IE204 Digital Design, Autumn 204 48