The Pennsylvania State University. The Graduate School. Department of Electrical Engineering ANALYSIS OF DC-TO-DC CONVERTERS

The Pennsylvania State University The Graduate School Department of Electrical Engineering ANALYSIS OF DC-TO-DC CONVERTERS AS DISCRETE-TIME PIECEWISE AFFINE SYSTEMS A Thesis in Electrical Engineering by Zhengbang Wang 214 Zhengbang Wang Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science August 214

The thesis of Zhengbang Wang was reviewed and approved* by the following: Jeffrey Mayer Associate Professor of Electrical Engineering Thesis Advisor Constantino Lagoa Professor of Electrical Engineering Kultegin Aydin Professor of Electrical Engineering and Department Head *Signatures are on file in the Graduate School

III ABSTRACT A boost dc-to-dc power converter has been among the application examples in several recent publications on stability analysis of piecewise affine systems (PAS). While those publications point to a great potential for PAS modeling and stability analysis of switch-mode power converters, the examples use a PAS model that is based on an incomplete generalized state space (GSS) model of the boost converter (here GSS refers to a piecewise-lti state space model and an accompanying set of state-, input-, and time-depent switching surfaces that determine the LTI model at any instant). In particular, the GSS model does not include the converter topology associated with discontinuous conduction mode (DCM) wherein the diode blocks reverse current while the switch is also off. The purpose of this thesis project is to re-examine the application of PAS modeling and stability analysis to power converters. To this, the converter modeling in the publications has been reproduced and then augmented to account for DCM. The state-space partitioning algorithm central to PAS stability analysis has also been imped in MATLAB and applied to the original and augmented models. Key words: piecewise affine system, stability analysis, state-space partition

IV TABLE OF CONTENTS List of Figures... VI Acknowledgements... IX Chapter 1 Introduction... 1 1.1 Motivation... 1 1.2 Contribution... 2 1.3 Organization... 3 Chapter 2 Conventional Models of dc-to-dc Converters... 4 2.1 Single Switch dc-to-dc Converters... 4 2.1.1 Step-Down (Buck) Converter... 4 2.1.2 Step-Up (Boost) Converter... 5 2.1.3 Buck-Boost Converter... 6 2.2 Periodic Steady State Analysis... 6 2.2.1 Continuous Conduction Mode... 7 2.2.2 Discontinuous Conduction Mode... 8 2.3 Generalized State Space Modeling... 8 2.3.1 Form of Generalized State Space Model... 9 2.3.2 Continuous Conduction Mode... 9 Example 1:... 11 2.3.3 Discontinuous Conduction Mode... 13 Example 2:... 14 2.4 Small Signal Modeling... 15 2.4.1 Analog Control of dc-to-dc Converters... 15 2.4.2 State Space Averaging... 17 2.4.3 Circuit Averaging... 18 2.4.4 Controller Design... 19 Example 3:... 19 Chapter 3 Discrete-Time Piecewise Affine Systems... 24 3.1 Discrete-Time Piecewise Affine Systems Modeling... 24 3.1.1 Discrete-Time Piecewise Affine System Representation... 24 3.1.2 Discrete-Time Piecewise Affine System Model Construction... 25 3.2 Definition of State Space Partition... 27 3.3 Algorithm to Obtain a State Space Partition... 28 3.3.1 State Space Partition without Disturbance... 28 Example 4:... 29 3.3.2 State Space Partition with Disturbance... 32 Example 5:... 32 Chapter 4 Piecewise Affine System Models of dc-to-dc Converters... 35 4.1 Derivation of Discrete-Time System Model... 35

V 4.1.1 Continuous-Conduction Mode... 36 4.1.2 Discontinuous-Conduction Mode... 37 4.2 Linearization of Discrete-Time Nonlinear Model... 39 4.2.1 Jacobian Matrix... 39 4.2.2 Linearization of Discrete-Time Equivalent System... 4 4.3 Piecewise Affine System Model of Boost Converter... 41 4.3.1 Piecewise Affine Model with Incomplete Diode Model... 41 4.3.2 Piecewise Affine System Model with Complete Diode Model... 43 4.4 Piecewise Affine System Modeling Guidelines... 45 4.4.1 Selection of Domains... 45 4.4.2 Selection of Operating Points... 46 4.5 Piecewise Affine System Controller Design... 46 Example 6:... 48 4.6 State Space Partition for Boost Converter with Incomplete Diode Model... 52 4.7 State Space Partition for Boost Converter with Complete Diode Model... 55 4.8 State Space Partition for Boost Converter with Disturbance... 59 4.9 Piecewise Affine System Analysis on Boost Converter Operating in DCM... 63 Chapter 5 Conclusion... 7 5.1 Summary... 7 5.2 Future Work... 7 Appix... 71 Test file... 71 partition_state_space... 74 partition_piecewise_affine_system_with_disturbance... 76 inequality_function_solver_r2_bounded... 8 simplify_vertex... 81 polygon2inequalities... 83 minterms_finder... 84 find_complementary... 89 M_generator... 92 plot_figure... 94

LIST OF FIGURES Figure 2-1. Schematic diagram of the buck converter.... 5 Figure 2-2. Schematic diagram of the boost converter.... 6 Figure 2-3. Schematic diagram of the buck-boost converter.... 6 Figure 2-4. Typically inductor current waveform for a converter operating in CCM.... 7 Figure 2-5. Typically inductor current waveform for a boost converter operating in DCM.... 8 Figure 2-6. Circuit topology of boost converter while switch is on.... 9 Figure 2-7.... Circuit topology of boost converter while switch is off and converter is operating in CCM.... 1 VI Figure 2-8. Transient response of boost converter using GSSM without diode reverse current blocking.... 12 Figure 2-9. Transient response of boost converter using GSSM without diode reverse current blocking relative to steady state.... 12 Figure 2-1. Circuit topology for boost converter while switch is off and the converter is operating in DCM.... 13 Figure 2-11. Transient response of GSSM with diode modeled completely.... 14 Figure 2-12. Transient response of GSSM with diode modeled properly relative to steady state 15 Figure 2-13. Schematic of boost dc-to-dc converter with voltage regulation.... 16 Figure 2-14. PWM controller. (a) Block diagram showing compensator amplifier and comparator. (b) Comparator signals.... 17 Figure 2-15. Bode plot of small signal model of closed-loop boost converter system.... 2 Figure 2-16. Step response of small signal model of closed-loop boost converter system.... 21 Figure 2-17. Step response of discrete time small signal model of closed-loop boost converter system. 21

VII Figure 2-18. Transient response of small signal modeling digital PWM boost converter.... 22 Figure 2-19. Transient response relative to steady state operating point.... 22 Figure 2-2. PWM duty ratio response.... 23 Figure 3-1. State space partitions D and D1.... 31 Figure 3-2. State-Space Partitions D3.... 31 Figure 3-3. Polytope of disturbance W for Example 5.... 33 Figure 3-4. D and D1 for Example 5.... 34 Figure 3-5. D1 for Example 5.... 34 Figure 4-1. Schematic of boost converter when operating in DCM. (a) Switch-on interval. (b) Switch-off interval. (c) Switch-off and diode-off interval.... 37 Figure 4-2. Transient response of piecewise affine model without diode reverse current blocking. 42 Figure 4-3. Transient response of piecewise affine model without diode reverse current blocking relative to steady state. (b) Enlarged view around steady state operating point.... 42 Figure 4-4. Transient response of piecewise affine model with complete diode model.... 44 Figure 4-5. (a) Transient response of piecewise affine modeling with diode modeled properly relative to steady state (b) Enlarged view of domain 3.... 44 Figure 4-6. State space switching sequence for PAS model with complete diode model.... 45 Figure 4-7. Operating points for linearization.... 49 Figure 4-8. Transient response of piecewise affine system model.... 5 Figure 4-9. Transient response of boost converter generalized state space model with complete diode model.... 51 Figure 4-1. Transient response of piecewise affine system model... 51 Figure 4-11. Transient response of boost converter generalized state space model with complete diode model.... 52

Figure 4-12. State space partitions of boost converter CCM.... 54 VIII Figure 4-13. State space partitions of piecewise affine system model with complete diode model. 58 Figure 4-14. Transient simulation of piecewise affine system model and generalized state space model. 59 Figure 4-15. Voltage error and current error between piecewise affine system model and generalized state space model.... 6 Figure 4-16. Several partitions and refinements of piecewise affine system.... 62 Figure 4-17. Transient response of GSSM with complete diode model operating in DCM.... 63 Figure 4-18. Steady state response of GSSM with complete diode model operating on DCM.... 64 Figure 4-19. Transient response of piecewise affine system model with complete diode model. 65 Figure 4-2. Transient response of piecewise affine system model with diode modeled completely relative to steady state.... 66 Figure 4-21. State space partitions of boost converter DCM.... 69

IX ACKNOWLEDGEMENTS I would like to thank Dr. Jeffrey Mayer who have helped and inspired me through the duration of my studies at the Pennsylvania State University.

1 Chapter 1 Introduction 1.1 Motivation Switch-mode power converters are widely used in consumer products as well as in industrial, medical, and aerospace equipment due to their high efficiency, low volume and weight, fast dynamic response, and low cost when compared to other methods for converting voltage and current levels between source networks and loads [1]. In the future they are also expected to be used extensively in electric vehicles and solar energy systems [2]. Although switch-mode power converters are inherently non-linear, hybrid dynamical systems due to the switching process, power converter control design has relied mainly on wellestablished methods from continuous-time linear systems theory, particularly s-domain transfer functions. To apply these analog control methods, small-signal models of a converter are derived using specialized linearization techniques such as state space averaging [3] or switch averaging [4]. In recent years, digital control of power converters has been of growing interest, because it offers greater programmability and robustness for the converter system, and because automated design tools t to neutralize an important advantage of the conventional methods, namely the facility with which most electrical engineers can applying them [5]. The discrete-time models of power converters required for digital control design are usually derived in a two-step process. First, the converter is modeled as a set of continuous-time piecewise LTI systems with state-, input-, and time-depent switching functions that determine whether a particular LTI model is appropriate or there should be a transition to a different LTI

2 model. Second, state-transition matrices are used to map the state at the beginning of a switching period to the state at the of the switching period. Owing to the form of the state transition matrices and the expressions for the switching functions, the resulting discrete-time model is nonlinear. A piecewise affine system (PAS) model has been proposed as a means to handle the nonlinear discrete-time model of power converters [6][7]. A PAS is a kind of hybrid dynamical system [8][9], as it is comprised of difference equations and discrete events. One approach to stability analysis for a PAS involves partitioning the state and input spaces into a finite number of non-overlapping convex polytopes, each of which corresponds to the domain for a linear or affine difference equation [9][1]. Piecewise affine system (PAS) can be used to simplify the simulation process of nonlinear systems by switching among several linearized subsystems for different operating regions [11]. Therefore, a simpler controller can be applied for the regulation of nonlinear system [12]. 1.2 Contribution We have reproduced the piecewise affine system modeling and stability analysis for a boost converter in [7]. In so doing, we have identified a limitation of the model in [7] and in an earlier paper [6] on which [7] is based. In particular, the original model does not account for diode reverse current blocking that arises in discontinuous conduction mode and during large transients. We have augmented the original model accordingly. We provide comparisons of the transient response of the boost converter using conventional small-signal models and generalized state space models as well as piecewise affine

3 system models. These comparisons are used to select the magnitude of the disturbance that is included in the piecewise affine system stability analysis. All of our results have been obtained using MATLAB codes that we have developed and included in Appix A. 1.3 Organization The reminder of the thesis is organized as follows. Chapter 2 reviews conventional modeling techniques used for single-switch power converters, such as small signal modeling and generalized state space modeling. Examples of each type of model are presented. Chapter 3 summarizes the definition, construction process, and sufficient conditions for stability of piecewise affine system symbolic models originally presented by Mirzazad-Barijough in [7]. The construction process and stability analysis are demonstrated using MATLAB codes developed indepently in this project. Chapter 4 reproduces the PAS modeling of a boost converter as in [7]. Furthermore, the PAS model is made more complete/accurate by including a circuit topology that was not modeled previously. Again, results are demonstrated using MATLAB codes developed indepently in this project. Chapter 5 spells out conclusions and recommations for future work.

4 Chapter 2 Conventional Models of dc-to-dc Converters This chapter introduces several common power electronic converters and conventional modeling methods used for them, such as small signal modeling and generalized state space modeling. The use of small signal models in conventional analog controller design is also demonstrated. A generalized state space model of a boost converter in which the diode is modeled completely is described. 2.1 Single Switch dc-to-dc Converters Single-switch dc-to-dc converters are widely used in regulated switch-mode dc power supplies and in dc motor drive applications [13]. They belong to a class of power converters for which a source of direct current is converted from one voltage level to another. There are three common types of single-switch dc-to-dc converters: step-down (buck) converter, step-up (boost) converter, and step-down/step-up (buck-boost) converter. 2.1.1 Step-Down (Buck) Converter As the name implies, a step-down or buck converter (Figure 2-1) provides a lower average output voltage V o = v o than its dc input voltage V d. For instance, buck converters are

5 used in computer power supplies to convert the 12-V main voltage down to the.8 1.8 V needed by the microprocessor, with an energy efficiency approaching 95%. S L Vd D C Ro vo(t) Figure 2-1. Schematic diagram of the buck converter. While the switch is on, the diode is reverse biased by the dc voltage source, and the inductor absorbs energy from the source, as V d > v o ; some of this energy is stored in the inductor and the rest is passed onto the load. When the switch is turned off, the diode turns on automatically to conduct the inductor current. While the diode is on, some of the energy stored in the inductor is delivered to the load. The capacitor is used to reduce ripple in the output voltage, so that v o V o. The voltage conversion ratio V o /V d deps on the duty ratio of the switch D = T on /T s where T s is the switching period and T on is on-time of the switch. An expression for the voltage conversion ratio is derived in Section 2.2. 2.1.2 Step-Up (Boost) Converter A step-up or boost converter (Figure 2-2) provides a higher average output voltage than its dc input voltage. When the switch is on, the diode is reverse biased by the capacitor, and the inductor absorbs energy from the dc voltage source V d. When the switch is turned off, the diode turns on automatically to conduct the inductor current. While the diode is on, some of the energy

6 stored in the inductor current is transferred to the load. The capacitor is used to reduce ripple in the output voltage. L D Vd S C Ro vo(t) Figure 2-2. Schematic diagram of the boost converter. 2.1.3 Buck-Boost Converter A buck boost converter (Figure 2-3) provides an average output voltage that may be lower than or higher than the dc input voltage. Its topology can be obtained by simplifying the cascade connection of a buck converter and a boost converter. S D Vd L C Ro vo(t) Figure 2-3. Schematic diagram of the buck-boost converter. 2.2 Periodic Steady State Analysis Periodic steady state analysis of a single-switch dc-to-dc converter is used to derive the voltage conversion ratio of the converter as a function of the switch duty cycle, and possibly, the

7 load current or resistance. Based on the form of the inductor current i L, a single-switch dc-to-dc converter can operate in two distinct modes: (1) continuous-conduction mode (CCM) and (2) discontinuous-conduction mode (DCM). 2.2.1 Continuous Conduction Mode il Ts IL t ton toff Figure 2-4. Typically inductor current waveform for a converter operating in CCM. Figure 2-4 shows a typical periodic steady-state inductor current waveform for continuous-conduction mode where i L > for all time. In the periodic steady state, the average inductor voltage must be zero. This also means that the energy into the inductor is equal to the energy out of the inductor over one period. The boost operating in CCM the voltage conversion ratio can be derived since in steady state the time integral of the inductor voltage in one period must be zero, V d t on + (V d V o )t off = dividing both sides by T s the voltage conversion ratio can be represented as, V o = T s = 1 V d t off 1 D

8 2.2.2 Discontinuous Conduction Mode A converter operates in discontinuous-conduction mode (DCM) when the diode blocks reverse current under light loading conditions. A typical DCM inductor current waveform is shown in Figure 2-5. In this mode, the average inductor current I L < I L 2, where I L is the maximum instantaneous inductor current. il IL t ton Ts Δ1Ts Δ2Ts Figure 2-5. Typically inductor current waveform for a boost converter operating in DCM. Based on the truth that integral of inductor voltage over one time period equal zero when operating in steady state V d DT s + (V d V o )Δ 1 T s = where Δ 1 T s means the time from switch off to current blocked. The voltage conversion ration can be expressed as, V o = Δ 1 + D V d Δ 1 2.3 Generalized State Space Modeling This section describes generalized state space modeling and applies it to the boost converter as an example. The model is also refined by adding a circuit topology corresponding to diode reverse current blocking.

9 2.3.1 Form of Generalized State Space Model The nonlinear dynamics of a power converter system can be represented by several linear time invariant (LTI) systems along with switching functions that define transitions from one LTI system to another. Each of the LTI systems corresponds to a circuit topology imposed by the conduction state of the switch and diode. Each of the switching functions is comprised of a linear combination of the state vector, input vector, and time. Assuming M circuit topologies, the LTI model, switching surface, and state vector map from topology m {1,.., M} to topology n {1,.., M}: x m = A m x m + B m u y = C m x m + D m u σ m (x m, u, d) = σ xm x m + σ um u + σ dm d + σ cm x n = R nm x m 2.3.2 Continuous Conduction Mode In CCM, there are only two circuit topologies to consider: switch on and switch off. The switch-on topology is shown in Figure 2-6. il(t) RL L vl(t) ic(t) Vd RC C Ro vo(t) Figure 2-6. Circuit topology of boost converter while switch is on.

1 A state-space representation of switch on topology can be derived by applying basic circuit analysis. The result is dv C [ dt ] = di L dt 1 (R o + R C )C [ R L L ] [ v C il ] + [ 1] V d L Thus, A 1 = 1 (R o + R C )C [ B 1 = [ 1] L R L L ] The switch-off topology is shown in Figure 2-7. il(t) RL L Vd vl(t) RC C ic(t) Ro vo(t) Figure 2-7. Circuit topology of boost converter while switch is off and converter is operating in CCM. The state-space representation is, dv C [ dt ] = di L dt 1 (R o + R C )C R o [ L(R o + R C ) R o (R o + R C )C 1 L (R R C R o L + L((R o + R C ) ) ] [ v C il ] + [ 1] v d L Thus,

11 A 2 = 1 (R o + R C )C R o [ L(R o + R C ) R o (R o + R C )C 1 L (R R C R o L + L((R o + R C ) ) ] B 2 = [ 1] L Example 1: Consider a boost converter as in [6], L = 1 μh, C = 5 μf, R L = 1 μω, R o = 3 Ω, V d = 1 V, V o = 5 V, T = 2 μs and apply the feedback control law as in [6], F = [.291.356] The duty ratio in the k th switching period is represented as d k = D + F[ x(kt s ) x ] where D = 1 V d /V o, x( kt s ) is the state vector at the start of the k th switching period ( of the last switching period), and x is the steady state operating point of the system. σ 1 (x 1, u, d) = d + (D + F[ x(kt s ) x ]) The switching surface for Topology 2 is σ 2 (x 2, u, d) = d + (D + F[ x(kt s ) x ]) The state vector maps are simply R 12 = R 21 = I The transient response of the generalized state space model of the boost converter without diode reverse current blocking is shown in the Figure 2-8.

12 Transient Response of Boost Converter Generalized State Space Modeling without Diode Reverse Current Blocking 1 v C (V) 5-5 1 i L (A) 5-5.5 1 1.5 2 2.5 3 3.5 4 d x 1-3 Figure 2-8. Transient response of boost converter using GSSM without diode reverse current blocking. The transient response relative to the steady state operating point is shown in Figure 2-9 and indicates that the system is stable. Transient Response Relative to Steady State Generalized State Space Modeling without Diode Reverse Current Blocking 1 i L - i L * 5-5 -1-8 -6-4 -2 2 4 6 8 * v C - v C Figure 2-9. Transient response of boost converter using GSSM without diode reverse current blocking relative to steady state. The inductor current in Figure 2-8 and Figure 2-9 goes below zero as a result of incomplete modeling of the diode, which should block reverse current.

13 2.3.3 Discontinuous Conduction Mode In DCM, there is a third circuit topology in which both the switch and the diode are off. This topology is shown in Figure 2-1. il(t) RL L vl(t) ic(t) Vd RC Ro vo(t) C Figure 2-1. Circuit topology for boost converter while switch is off and the converter is operating in DCM. The state-space representation is, Thus, [ dv C dt ] = [ 1 (R o + R C )C ] [v C ] + [ ]E 1 A 3 = [ (R o + R C )C ] B 3 = [] i L (t) = The switching surface for Topology 2 must be modified and a switching surface for Topology 3 must be defined: σ 2 (x 2, u, d) = d + (D + F[ x(kt s ) x ]) σ 3 (x 3, u, d) = d + (D + F[ x(kt s ) x ]) The additional state vector maps are

14 R 32 = [1 ] R 13 = [ 1 ] Example 2: When modeling the converter with a diode reverse current blocking, the transient response of the boost converter is simulated in Figure 2-11. 1 Transient Response of Boost Converter Generalized State Space Modeling with Diode Modeled Properly v C (V) 5-5 15 1 i (A) L 5-5.2.4.6.8.1.12 t Figure 2-11. Transient response of GSSM with diode modeled completely. The simulated transient response relative to steady state in Figure 2-12 indicates the system is stable. We can find the current will not drop below zero in Figure 2-11 and Figure 2-12 by modeling the diode properly. It is a more accurate modeling approach than the model in [6] and [7].

15 Transient Response Relative to Steady State Generalized State Space Modeling with Diode Modeled Properly 14 12 1 i L - i L * 8 6 4 2-2 -1-8 -6-4 -2 2 4 6 8 * v C - v C Figure 2-12. Transient response of GSSM with diode modeled properly relative to steady state. 2.4 Small Signal Modeling Small signal analysis has appeared in the power electronics literature in various forms [14]: state space averaging, switch averaging, and dynamic phasors. The main purpose of small signal models is to permit the use of well-established control design methods for linear systems. Small signal analysis is the study of deviations from an operating point for a system subjected to small disturbances [15]. The prerequisite condition of this method is that the disturbances are small enough that the deviation of the system can be described linearly. 2.4.1 Analog Control of dc-to-dc Converters In most dc-to-dc converter applications, the average output voltage must be regulated (Figure 2-13) to a desired level in spite of disturbances in the input voltage V d or output load R o.

16 il(t) RL L Vd vl(t) PWM ic(t) C Ro vo(t) Controller Vo_ref Figure 2-13. Schematic of boost dc-to-dc converter with voltage regulation. In a single-switch dc-to-dc converter, the average output voltage is controlled by controlling the switch on and off time. The most common method of regulation utilizes pulsewidth modulation (PWM) in which the switch is turned on periodically, but the duration of the on-time each period (i.e., the duty cycle) may change from period to period. The PWM control signal is usually generated by comparing a control voltage v control to a sawtooth waveform as shown in Figure 2-14.

17 Vref Vo Amplifier vcontrol Sawtooth Comparator PWM (a) Sawtooth Waveform vcontrol On Off (b) Figure 2-14. PWM controller. (a) Block diagram showing compensator amplifier and comparator. (b) Comparator signals. The V control signal is generated by the compensator amplifier which is designed based on the small signal model of power converter. 2.4.2 State Space Averaging The State Space Averaging method was the first formal method for small signal modeling of power converters [3]. The averaged state space model is obtained by a weighted summation of the state matrices. The weight of each matrix is determined by the PWM switch on and off time:

x = (da 1 + d A 2 )x + ( db 1 + d b 2 )V d (2.1) 18 y = (dc 1 T + d c 2 T )x where d = T on /T s, d = T off /T s, T on and T off are switch time intervals, and T s is the switching period. The system described by (2.1) can be perturbed, by introducing a perturbation of input voltage V d and/or duty ratio d. Then the dc and ac solutions are obtained in following form [3]: X = [DA 1 + (1 D)A 2 ] 1 [Db 1 + (1 D)b 2 ]V d Y = [Dc 1 + (1 D)c 2 ]X x = [DA 1 + (1 D)A 2 ]x + [Db 1 + (1 D)b 2 ]V d + [(A 1 A 2 )X + (b 1 b 2 )V d ]d y = [Dc 1 + (1 D)c 2 ]x + [(A 1 A 2 )X + (b 1 b 2 )V d ]d Although the State Space Averaging method allows us to ext standard dc and ac circuit analysis techniques to switching circuits and transient analyses can also be run much faster by using State Space Averaging models. However by applying State Space Averaging, we ignore the cycle-by-cycle switching and looking at the average characteristics of the circuit at frequencies below half the switching frequency. We lose the ability to see switching ripple or actual switching waveforms. 2.4.3 Circuit Averaging Circuit averaging is an approach that relate average voltages and currents at two ports associated with a transistor-diode pole used to implement any of the basic dc-to-dc converters. The small signal transfer function for boost converter can be derived as [16],

19 v o d = v ( sr L C + 1)( s d ( 1 D ) 2 L eq R o + 1) s 2 L eq C + s ( R L C + L eq R ) + 1 L eq = 1 (1+D ) 2 L. Zeroes of the plant transfer function are ω z1 = 1 R L C, ω z2 = R o L eq. Notice that ω z1 is in the right half plane (RHP). The complex-conjugate poles of the plant transfer function have frequence ω o = 1 L eq C. 2.4.4 Controller Design A voltage-mode controlled boost converter operating in continuous conduction mode (CCM) should be designed concerning the boost converter s inherent RHP zero. Example 3: Consider a boost converter as in [6] in Example 1. We set compensator zeroes and poles, ω z1c = ω z2c =.6 ω p1, ω p1c = ω z2 (cancel RHP pole), ω p2c = ω p1c. Small signal modeling voltage compensator for boost converter operating on CCM. T compensator (s) = 5.756 1 4 s2 + ( ω z1c + ω z2c )s + ω z1c ω z2c s 3 + ( ω p1c + ω p2c )s 2 + ω p1c ω p2c The closed-loop transfer function for the system is = 5.756 14 S 2 2.32 1 7 s + 1.658 1 12 s 3 + 2.4 1 5 + 1.44 1 1

H(s) = 5.996 1 1 s 4 11.99s 3 + 1.444 1 6 s 2 + 9.21 1 8 s + 4.144 1 13 1.25 1 8 s 5 +.38s 4 + 171s 3 + 1.84 1 6 s 2 + 1.348 1 1 s + 4.144 1 13 The Bode plot of the compensated boost converter is shown in Figure 2-15. The corner frequency is seen to be ω c = 2 1 4 Hz and the phase margin is 63, which should be adequate to ensure stability even in the presence of disturbances. 2 5 Boost CCM: Bode Plot of T p, T c, T ol, and T cl Magnitude (db) -5-1 -15 36 Phase (deg) 27 18 9 1 2 1 3 1 4 1 5 1 6 1 7 Frequency (Hz) Figure 2-15. Bode plot of small signal model of closed-loop boost converter system. The step response of the compensated boost converter is shown in Figure 2-16. The system has overshoot of 3% and setting time of 1.2 ms, which satisfies the common performance requirement.

21 1.4 Step Response for Continuous Model Amplitude 1.2 1.8.6.4.2 -.2 1 2 3 4 5 6 7 8 Time (seconds) x 1-4 Figure 2-16. Step response of small signal model of closed-loop boost converter system. Zero-order hold equivalent discrete compensator transfer function can be represented as, T compensator_d =.141z 2.269z +.147 z 3 1.181z 2 +.1897z.823 The step response of the discrete-time model is shown in Figure 2-17, which demonstrates that the controller is also stable in discrete time domain with a sample time of T s = 2 1 6 s. 1.4 Step Response for Discrete Model Amplitude 1.2 1.8.6.4.2 -.2 1 2 3 4 5 6 Time (seconds) x 1-4 Figure 2-17. Step response of discrete time small signal model of closed-loop boost converter system.

22 The simulation of the small signal modeling controller and boost converter is developed with the parameters in last section (shown in Figure 2-18). It operates in the steady state with V o = 5 V when the reference output voltage steps by.5 V to 5.5 V the system can have a right response to 5.47 V. 6 Transient Response of Converter over Several Periods 5.5 v (V) C 5 4.5 8 6 i (A) L 4 y transitions y waveform 2.2.4.6.8.1.12.14.16.18.2 s Figure 2-18. Transient response of small signal modeling digital PWM boost converter. The transient response relative to the steady state operating point is shown in Figure 2-19 and indicates that the system is asymptotically stable. Transient Response of Converter over Several Periods.6 y transitions.5.4 i L (A).3.2.1 -.1 -.2 -.1.1.2.3.4.5.6 v (V) C Figure 2-19. Transient response relative to steady state operating point.

23 Figure 2-2 shows the PWM duty ratio response by the voltage regulation which illustrates that the controller is stable..82 PMW duty ratio.815 d.81.85.8.795.2.4.6.8.1.12.14.16.18.2 t(s) Figure 2-2. PWM duty ratio response.

24 Chapter 3 Discrete-Time Piecewise Affine Systems This chapter summarizes the definition of discrete-time piecewise affine systems and the stability analysis of such systems as presented in [7]. Several of the examples in [7] are reproduced using indepently developed MATLAB codes. These codes will be used to analyze the stability of a dc-to-dc boost converter in the next chapter. 3.1 Discrete-Time Piecewise Affine Systems Modeling This section echos the definition of a discrete-time piecewise affine system and a corresponding symbolic model used for stability analysis from [7] and [ 错误! 未定义书签 ]. 3.1.1 Discrete-Time Piecewise Affine System Representation A discrete-time piecewise affine system (without disturbances) can be defined as follows [17]. Suppose n, m, l, N N are given, S = {(A 1, B 1, b 1, C 1, D 1, d 1, ),, (A N, B N, b N, C N, D N, d N )} (3.1) where A 1,, A N R n n, B 1,, B N R n m, b 1,, b N R n, C 1,, C N R l n, D 1,, D N R l m and d 1,, d N R l. Let D = {D 1,, D N } (3.2)

be a partition of R n into N nonempty cells such that N i=1 D i = R n and D i D j = whenever i j. Then the pair (S, D) defines the discrete-time piecewise affine system represented by 25 x[k + 1] = A θ[k] x[k] + B θ[k] u[k] + b θ[k], k N o (3.3) y[k] = C θ[k] x[k] + D θ[k] u[k] + d θ[k], k N o for any initial state x[] R n, where the switching sequence is θ = (θ(), θ(1), ) is such that θ[k] = i whenever x[k] D i. 3.1.2 Discrete-Time Piecewise Affine System Model Construction The main purpose of introducing symbolic model construction is to abstract the behavior of the continuous, infinite piecewise affine system by a discrete, finite model. The symbolic model can then be used for stability analysis via a partition of the state space. In particular, if the partitioning process leads to an invariant subdomain with a corresponding stable linear (not affine) difference equation, the system is stable according to the Theorem 3 of [7]. In the case of power converters, the piecewise affine system is obtained via linearization of a nonlinear model at selected operating points. Consequently, the piecewise affine system is an approximate model of original system. We consider this to be a source of modeling error and treat it as a disturbance in the piecewise affine system model. To incorporate the disturbance in the partitioning process, we rely on the definition of Minkowski sum of two sets A and B: A B = {a + b: a A, b B} The first symbolic model S 1 is defined as follows: Let D be the original state space partition and define a vertex set of the state space partition as V = {1,, N} where N is the number of subdomains in D. Now for each (i, j) V 2, the refinement of D can be derived by

26 D (i,j) = {x D i : A i x + b i D j ( B j W)} (3.4) In other words, D (i,j) is the set of all states x[k] in subdomain D i that map into states x[k + 1] that are in subdomain D j with disturbance w(t) W. A reverse search technique [18] can be used to compute each nonempty set D (i,j) where (i, j) V 2. Now, define an edge set of the state space partition as E = {(i, j) V 2 D (i,j) } and directed graph as G = (V, E ). Also, define the switching sequence M i = {i} for each i V and the set M = {M i : i V }. Then S = (D, G, M ) is constructed as the initial symbolic model of the piecewise affine system (S, D). With S and the refinement of D, D 1 = {D (i,j) (i, j) E } we can construct the next symbolic model. Supposing D L+1 is a refinement of the partition D L with disturbance W, the subdomains in D L+1 may overlap each other. To obtain a valid non-overlapping partition D L+1, a mintermbased method can be used to obtain the coarsest, convex polyhedral partition that is compatible with D L. The set of switching sequences represented by the serial number of the original partition D to each i V L+1 can be represented by M i = {(i,, i L+1 ) V L+2 : (i,, i L ) M j, (i 1,, i L+1 ) M k, D i D (j,k), (j, k) E L } (3.5) with M L+1 = {M i i V L+1 } and G L+1 = (V L+1, E L+1 ). The symbolic model S L+1 = {D L+1, G L+1, M L+1 } is thus obtained. The algorithm for constructing a symbolic model can be summarized as follows: 1. Let L =, D = {D 1,, D N }, V = {i: D i D }, M i = {i} for each i V and M = {M i : i V }. 2. For each (i, j) V L 2, construct D (i,j) as function (3.4). Let E L = {(i, j): D (i,j) } and D L+1 = {D (i,j) : (i, j) E L }.

27 3. Output S L = {D L, G L, M L } and D L+1. 4. Obtain the coarsest partition of D L+1. 5. Let V L+1 = {maxv L + 1,, maxv L + D L+1 }. 6. For each i V L+1 obtain M i as in (3.5) and let M L+1 = {M i : i V L+1 }. 7. Increment L to L + 1 and go to Step 1. 3.2 Definition of State Space Partition In mathematics, space partitioning is the process of dividing a space into two or more disjoint subsets. This section describes a procedure for recursively refining the state-space partition while representing the switching sequence of the domain specified by the initial partition of the state space. If a piecewise affine system is stable, the partition procedure will terminate after a finite number of steps when the partition keeps identical with unique subdomain switching sequence. At the same time, the affine term of the unique subdomain should be all zeroes [7]. Let S and D be as in (3.1) and (3.2), so the symbolic model (S, D) defines a piecewise affine system of the form (3.3). Define D i (Q) = Q D i for i {1,, N} and D (i,,i L )(Q) = {x D (i,,i L 1 )(Q): A i x + b i D (i1,,i L )(Q)} (3.6) recursively for L N and (i,, i L ) {1,, N} L+1, so that D (i,,i L )(Q) is the set of all states in D (i,,i L 1 )(Q) Q that will jump into the region D (i1,,i L )(Q) Q in one step. Using this approach, the initial state space partition of Q is D (Q) = {D 1 (Q),, D N (Q)}, For each L N, the state space partition

28 D L (Q) = {D (i,,i L ) (Q): (i,, i L ) {1,, N} L+1 } contains all D (i,,i L )(Q) that are nonempty and can be call L path partition of Q. 3.3 Algorithm to Obtain a State Space Partition 3.3.1 State Space Partition without Disturbance Considering there is no disturbance W, a nonempty partition polyhedron set D (i,,i L+1 ) that belongs to L + 1 path partition by the definition (3.4), can be interpreted as a set of inequality functions R (i,,i L ) r (i,,i L ) [ ] x + [ R (i1,,i L+1 )A i R (i1,,i L+1 )b i + r ] < (3.7) (i1,,i L+1 ) The first inequality functions R (i,,i L )x + r (i,,i L ) < represent the state vector that belongs a region of the state space of L path partition with switching sequence(i,, i L ). The second inequality functions R (i1,,i L+1 )(A i x + b i ) + r (i1,,i L+1 ) < indicate that the state vector x in both domain i and D (i,,i L ) can switch into the area of L path with switch sequence(i i,, i L+1 ). Therefore, by solving the combined inequality functions (3.7), we can get the subdomain of state space belongs to L + 1 path with switching sequence(i,, i L+1 ). Each non-empty domain of the state space partition can be represented by polytope whose vertices can be determined by solving the inequality functions (3.7). In the case of R 2, the polytope is actually just a polygon that can be determined by the following algorithm: 1. Treat each inequality function entry as an equation that can be represented as a line in the state space plane. 2. Calculate all intersections of the lines. 3. Keep all the intersections that satisfy the inequality functions of (3.7).

29 As in [19], we can draw a conclusion that D L (Q) is invariant if partition pattern is the same as D L+1 (Q). Example 4: Consider the system (S, D) of Example 5 in [7] with N = 3, where S is defined by, A 1 = [ 1 4 1 1 ], b 1 = [ ] 4 A 2 = [ 1 1 ], b 2 = [ 4 2 ] A 3 = [ 5 2 1 2 1 2 5 2 ], b 3 = [ 1 ] and D is D 1 = {[x 1 x 2 ] T R 2 x 1 x 2 < 2, x 1 + x 2 }, D 2 = {[x 1 x 2 ] T R 2 x 1 + x 2 <, x 1 < 1}, D 3 = {[x 1 x 2 ] T R 2 x 1 x 2 2, x 1 1}. The original domains above can be represented by translating the definition of D into inequality functions as, D i : R i x < k i, i {1,2,3} R 1 = [ 1 1 1 1 ], k 1 = [ 2 ] R 2 = [ 1 1 1 ], k 2 = [ 1 ]

3 R 3 = [ 1 1 1 ], k 3 = [ 2 1 ] Then the partition D (i,j) polygon can be obtained by solving the inequality functions D (i,j) = {x D i : A i x + b i D j } which is also R i x < k i { R j (A i x + b i ) < k j with the algorithm given above. D (i,j) indicates an action in which state vector [x 1 x 2 ] T R 2 switches from subdomain D i to subdomain D j in one step from the initial partition of state space. The Figure 3-1 demonstrates the 1 path partition that indicates the switching sequence. For example, subdomain D 11 is the area that includes state vectors that switch from subdomain D 1 to (the same) subdomain D 1, while D 12 is the area that includes state vectors that switch from subdomain D 1 to subdomain D 2. In this particular system, the state vector cannot switch from subdmain D 1 to subdomain D 3, so there is no subdomain D 13 in Figure 3-1.

31 4 D 1 3 2 1 D22 D11 D12-1 -2-3 D21 D31 D33-4 -4-2 2 4 (a) D (b) D 1 Figure 3-1. State space partitions D and D 1. Similarly, the state space partition D ijk of 2 path partition of Q can be calculated by solving inequality functions, R ij x < k ij { R jk (A i x + b i ) < k jk 4 D 2 3 2 1 D221 D112 D121-1 -2-3 D212 D312 D333-4 -4-2 2 4 Figure 3-2. State-Space Partitions D 3.

32 For example, in Figure 3-2 D 112 is the area that includes a state vector that can switch from subdomain D 1 to subdomain D 1 and then to subdomain D 2 in a 2 path. The state space partition is identical to the result of Example 5 in [7] indicating that the state space partitioning algorithm has been implemented correctly 3.3.2 State Space Partition with Disturbance Suppose disturbance W is represented as the vertices of a polytope, by the definition of Minkowski sum the subdomains can be derived from (3.7) by enlarging the domains which process is demonstrated in the Example 5. Example 5: Given a system (S, D) of Example 4 in [7] with N = 3, where S and D is defined by, A 1 = [ 1 2 3 2 ], b 1 = [ ] 1 2 A 2 = [ 1 4 1 ], b 2 = [ ] 1 2 A 3 = [ 2 1 3 ], b 3 = [ 1 1 ] B 1 = B 2 = B 3 = [ 1 1 ] and D 1 = {[x 1 x 2 ] T R 2 x 1 1},

33 D 2 = {[x 1 x 2 ] T R 2 1 < x 1 < 1}, D 3 = {[x 1 x 2 ] T R 2 1 < x 1 }. The boundary Q is represented by a polygon with vertices [4 2] T, [ 4 2] T, [ 4 2] T and [4 2] T. The disturbance W is represented by polygon with vertices [2 2] T, [ 2 2] T, [ 2 2] T and [2 2] T. 3 Disturbance 2 1 i L - i L * -1-2 -3-4 -3-2 -1 1 2 3 4 * v C - v C Figure 3-3. Polytope of disturbance W for Example 5. To approach the reverse search method we can simplify the influence of the disturbance by enlarging the subdomains, D 1 = {[x 1 x 2 ] T R 2 x 1 1 + 2}, D 2 = {[x 1 x 2 ] T R 2 1 2 < x 1 < 1 + 2}, D 3 = {[x 1 x 2 ] T R 2 1 2 < x 1 }. Then the original domain and state space partition are shown in Figure 3-4. In Figure 3-4, D 1 is a refinement of D which means that initial states in a particular domain of D 1 transition to a particular domain in the original partition D. For example, the initial states in subdomain D 12 transition from subdomain D 1 to subdomain D 2 in one period. D 1 is derived by finding all

34 the minterms of D 1. For example, in Figure 3-5 subdomain D 6 is the overlap area of D 23, D 22, D 21. It indicates that initial state vectors in subdomain D 6 can switch from D 2 to D 3, D 2 or D 1 because the disturbance. The state space partition result is slightly different from Example 5 in [7] result in D 1 and D 3 due to the partition boundary Q for exhibition briefly. However the D 2 region is the same with Example 4. (a) D (b) D 1 Figure 3-4. D and D 1 for Example 5. Figure 3-5. D 1 for Example 5.

Chapter 4 Piecewise Affine System Models of dc-to-dc Converters The stability analysis of dc-to-dc converters modeled as piecewise affine systems is presented in this chapter. The model construction and state space partitioning procedure described in [7] are reproduced. Those results are then exted to a model of the converter that includes diode reverse current blocking in the discontinuous-conduction mode. State space partitions are generated to analyze the stability of the original model and of the more complete model. Finally, the approximation error of the piecewise affine system model relative to the generalized state space model is used to select the extent of the disturbance to include in a regeneration of the state space partition. 4.1 Derivation of Discrete-Time System Model This section presents the derivation of two non-linear discrete-time state space models for the boost converter. The first model matches [7] but is based on an incomplete modeling of the diode in discontinuous conduction mode. The second model includes the proper behavior of the diode during reverse blocking but utilizes a Taylor series approximation for determining the start of the reverse blocking interval.

36 4.1.1 Continuous-Conduction Mode Using x(kt s ) to represent the initial state in the k th switching period and x((k + d k )T s ) to describe the intermediate state when the switch turns off during that switching period, the response of the system operating in continuous-conduction mode (CCM) can be expressed as x((k + d k )T s ) = Φ 1(d k )x(kt s ) + Γ 1(d k ) x((k + 1)T s ) = Φ 2(d k )x((k + d k )T s ) + Γ 2(d k ) where expressions for Φ 1, Φ 2, Γ 1 and Γ 2 can be derived from the appropriate continuous-time state space representation as the sum of the zero-input response and zero-state response. (k + 1)T s x((k + 1)T s ) = e AT sx(kt s ) + e A((k + 1)Ts τ) Bu(τ)dτ kt s In particular, Φ 1(d k ) = e A 1d k T s d k T s Γ 1(d k ) = e A 1(t τ) B 1 u(τ)dτ Φ 2(d k ) = e A 2(1 d k )T s (1 d k )T s Γ 2(d k ) = e A 2(t τ) B 2 u(τ)dτ From these, a non-linear discrete-time state space representation can be written as where x[k + 1] = Φ (d k )x[k] + Γ (d k ) Φ (d k ) = Φ 2(d k )Φ 1(d k ) Γ (d k ) = Φ 2(d k )Γ 1 (d k ) + Γ 2 (d k )

37 A control law to determine d k based on the value of the state vector at the of the previous switching period will be introduced later. 4.1.2 Discontinuous-Conduction Mode In discontinuous-conduction mode (DCM), the inductor current i L ramps down to during the switch-off interval, but the diode prevents the current from going negative. That is, the diode turns off, so there is a third circuit topology as shown in Figure 4-1. The output capacitor continues to discharge though the load resistance. The state space representation is more complicated for discontinuous-conduction model, because the switching period is comprised of three intervals instead of two, and the transition between the Interval 2 and Interval 3 is state depent. il(t) RL L il(t) RL L vl(t) ic(t) vl(t) ic(t) Vd RC C Ro vo(t) Vd RC C Ro vo(t) (a) (b) il(t) RL L vl(t) ic(t) Vd RC Ro vo(t) C (c) Figure 4-1. Schematic of boost converter when operating in DCM. (a) Switch-on interval. (b) Switchoff interval. (c) Switch-off and diode-off interval.

38 The circuit topology during Interval 1 is shown in Figure 4-1-(a). The response during this interval is already known to be d k T s x((k + d k )T s ) = e A 1d k T s x(kt) + e A 1(t τ) B 1 u(τ)dτ where d k is based on the value the state vector at the of the previous switching period. During Interval 2 (Figure 4-1-(b)), the switch is off, the diode is on, and the inductor current ramps down. The response can be represented as x((k + d k + σ)t s ) = e A 2σT s x((k + d k )T s ) + σt s e A 2(σT s τ) B 2 u(τ)dτ (4.1) where σ < 1 d k indicates the duration time of Interval 2. The system enters Interval 3 when the inductor current reaches zero and the diode turns off to block reverse current. The time σ and capacitor voltage v C ((+d k + σ)t s ), at the of Interval 2 can be solved for from (4.1) given i L ((k + d k + σ)t s ) =. Equation (4.1) is a transcental equation in σ, so we utilize a Taylor series expansion about point σ o = 1 (1 d 2 k). During Interval 3, the inductor current i L remains at zero and the capacitor continues to discharge through the load resistor. With the resulting σ and the capacitor voltage v C ((k + d k + σ)t) at the of Interval 2, the state at the of switching period can be expressed as v C ((k + 1)T s ) = exp ( 1 RC (1 d k σ)t s ) v C ((k + d k + σ)t s ) i L ((k + 1)T s ) =

39 4.2 Linearization of Discrete-Time Nonlinear Model In mathematics, linearization means to find a linear approximation to a function at a given point. In the study of dynamical systems, linearization is a method for assessing the local stability of an equilibrium point of a system of nonlinear differential equations or discrete dynamical systems [2]. With the state-space representation of both CCM and DCM discrete-time nonlinear model, the approach of linearization is shown in this section. 4.2.1 Jacobian Matrix The Jacobian matrix is an important matrix of analysis nonlinear system. If the function F(x) is differentiable at a point p = ( x 1,, x n ), then the Jacobian matrix defines a linear map R n R n, which is the linear approximation of the function F(x) near the point p. The Jacobian matrix is defined as J F ( x 1, x 2,, x n ) = F x x o = F 1 F 1 F 1 x 1 x 2 x n F 2 F 2 F 2 x 1 x 2 x n F n F n F n [ x 1 x 2 x n ] F(x) F(x o ) + J F (x o )(x x o ) + o( x x o ) x = x o With the Jacobian matrix, the nonlinear model of boost converter can be linearized at operating points of interest.

4 4.2.2 Linearization of Discrete-Time Equivalent System The linearization approach can be represented by following steps, where F(x) is the state space representation of boost converter, x is the state vector of last operating period. y = F(x) F(x) xo + F x x o (x x o ) x = x x o y = y x o y + x o F(x) xo + F x x o x y F x x o x + F(x) xo x o y + x F x x o (x + x x o ) + F(x) xo y F x x o x + F(x) xo + F x x o (x x o ) x The piecewise affine model can be represented as where y A xo x + B xo A xo = F x x o B xo = F(x) xo + F x x o (x x o ) x.

41 4.3 Piecewise Affine System Model of Boost Converter This section compares the piecewise affine system model of the boost converter without modeling of diode reverse current blocking as in [7] and with modeling diode reverse current blocking. 4.3.1 Piecewise Affine Model with Incomplete Diode Model Take the piecewise affine model of [7] x[k + 1] =.466.715 [ 2.3361.413 ] x[k] + [ 1.5657 ] 13.7547 if Fx[k] <.4,.8621.891.747 [ ] x[k] + [ ] 1.3648.2376 4.951 if.4 Fx[k] <.1,.9667.741. [ ] x[k] + [ ].6847.6266. if.1 Fx[k] <.1, 1.36.563.193 { [ ] x[k] + [ ].2216.9229 2.7743 if Fx[k].1 The operating points used for linearization are not given in [7], so we determined them by minimizing the norm of the difference between the linearized model and the given piecewise affine system matrices. The operating points relative to steady state were determined to be x o1 = [ 2.5954 2.555 ], x o2 = [ 9.9928 1.9469 ], x o3 = [ ], x o4 = [ 1.1.26 ]. The transient response of the piecewise affine system model without diode reverse current blocking is shown in Figure 4-2.

42 8 Response for Piecewise Affine Modeling without Diode Reverse Current Blocking 6 v C (V) 4 2 8 6.5 1 1.5 2 2.5 3 3.5 4 x 1-3 i L (A) 4 2.5 1 1.5 2 2.5 3 3.5 4 t x 1-3 Figure 4-2. Transient response of piecewise affine model without diode reverse current blocking. Figure 4-3 shows the trajectory of the transient response of the piecewise affine system model without diode reverse current blocking relative to the steady state operating point x*=[5.235.323] T. The red dashed line in Figure 4-3 is introduced to indicate when the inductor current i L equals to or saturate zero. Transient Response Relative to Steady State Piecewise Affine Modeling without Diode Reverse Current Blocking 8 Transient Response Relative to Steady State Piecewise Affine Modeling without Diode Reverse Current Blocking 1.2 7 D3 1 i L - i L * 6 5 4.4 3.2 2 -.2 1 D4 D3 D2 D1 -.4 -.6-1 -6-4 -2 2 -.5.5 * v C - v C * v C - v C Figure 4-3. i L - i L *.8.6 Transient response of piecewise affine model without diode reverse current blocking relative to steady state. (b) Enlarged view around steady state operating point.