Australian Journal of Basic and Applied Sciences

ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 ISSN:99-878 ustralian Journal of asic and pplied Sciences Journal home page: www.ajbasweb.com Frame of Reversible dder and arry Skip dder and Optimization Using New Reversible Logic s for Quantum-ot ellular utomata Neeraj Kumar Misra, 2 Subodh Wairya, 3 V.K. Singh,2,3 stitute of Engineering and Technology, Electronics Engineering department, Lucknow, dia R T I L E I N F O rticle history: Received 28 ugust 25 ccepted 5 September 25 vailable online 5 October 25 Keywords: Reversible logic, Reversible adder, arry Skip adder, Garbage Output,Quantum cost, Quantum-dot cellular automata. S T R T Objective: Reversible logic has become more prominent in the field of low power nanotechnology era. It has specially used inquantum-dot cellular utomata (Q) which substituted the MOS technology. designing with MOS it requires a large layout area in making the contacts between the different devices. This work demonstrates the reversible adder and carry skip adder circuit based on three new type of reversible gates, namely, Full adder subtraction (FS), Half adder subtraction (HS) and Overflow detection (O) gates, to optimize the adders circuit. The new type of reversible full adder using FS gate is best circuit in terms of quantum cost. y utilizing these three new types of gates, reversible n-digit adder and - digit carry skip adder are also proposed with its algorithm. addition, lower value of reversible parameters has been presented and has more influence on reducing the circuit cost which is far lower. This O gate is first ever gate layout design implemented in the Q and that layout in Q provided, the more suitable simulation waveform for overflow detection. lso,the realization of the O gate with Q results in minimum cell complexity, clock cycle delay (latency) and area which are found to be 74, 3 and.27µm 2 respectively. rea and delay analysis also show that the circuits is optimized in terms of architectural complexity and speed. 25 ENSI Publisher ll rights reserved. Toite Thisrticle: Neeraj Kumar Misra, SubodhWairya and V. K. Singh, Paper title.frame of Reversible dder and arry Skip dder and Optimization Using New Reversible s for Quantum-ot ellular utomata. ust. J. asic & ppl. Sci., 9(3): 286-298, 25 INTROUTION Reversible logic has the popular perspective of designing digital logic operation with negligible power consumption. It is explained by Landauer that the loss of each bit of information dissipates heat energy KT ln2 joules, where T is temperature and K is the oltzmann s constant (Landauer, 96). Sometime on ennett explain that the energy losses could be prevented, if the logic computation is turn to reversible way (ennett, 973). reversible circuit is designed by reversible gates. reversible gate expression, it computes is bijective, that is, every distinct input pattern yields a distinct output pattern (ibhash Sen et al, 23; Guown yang et al, 25;M.Mustafa et al, 23; Neeraj Kumar Misra et al, 25). Presently Quantum-dot ellular utomata (Q) become an attractive research area due to high computing speed, low power and high device density in nano-electronics digital circuits (ibhash Sen et al, 25; li Newasbaharet al, 25). Q cell formation of four quantum dots placed at the corner of a square and comprise two free electrons (Shaahinangiziet al, 24). Q logic state is laid down by the polarization of electrons. The two stable polarization of electrons are binary logic (P= -) and binary logic (P=) as depicted in Fig. e. The timing in Q is versed by the synchronized of four clock zones and each clock zone has 9 phase shift as depicted in Fig f. The fundamental Q layout design are the three input majority voter gate (MV) and an inverter, depicted in Fig b, c. The majority voter gate described as MV(,,)=++. We look into that majority vote (MV) is the optimum preference in designing of logic design such as N, OR as depicted in Fig. d, h. rithmetic circuits like binary dder/subtraction are the essential blocks of digital circuit design (Himanshuthapliyalet al, 28;Majid Haghparastet al, 28;. Krishnaveniet al, 2). This essential blocks is mostly used in digital signal processing (SP) application like convolution, Fast Fourier transform (FFT) and orresponding uthor: Neeraj Kumar Misra, epartment of Electronics Engineering, stitute of Engineering and Technology, Lucknow, dia. E-mail id: neeraj.mishra@ietlucknow.ac.in

287 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 Laplace etc. The rest of the paper is organized as follows: Section 2 is dedicated to the preliminary approach of adder. The proposed three new types of reversible gates and there quantum circuitsare presented in Sub-section 3.. Section 3.4, Tunnelling Potential related work on this adder and various design issue lemmas are reported. The carry skip adder design procedure is reported in Section 3.5. Section 4, deals with proposed O gate layout and simulation result in Q framework. inary, P= - (a) Quantum Well M aj Junction Tunnel MV M aj Localised 9 Electron 45 (e) inary, P= + Switch 2 Hold 3 Release 4 Relax (b) (f) (c) (g) Wire-crossing Y Y Y Y (d) P= - (h) P= Fig. : Q fundamentals (a) Quantum cell (b) Q Majority voter(c) Q verter(d) Q, N gate(e) Four-dot Q cell with two different polarization (f) Q clock (g) Q Wire(h) Q, OR gate. 2. ackground Study: Several efforts have already been constituted to design of reversible adder and carry skip adder.preparatory, a reversible adder was presented by shish Kumar iswas et al.[28]. The design was based on the novel MTSG gate. The adder circuit consist of gate count, garbage output and 55 quantum cost. Rigui Zhou et al. [22],a design frame the adder, based on novel ZRQG gate and NG gate was designed. This adder requires 8 gate count, garbage output and 54 quantum cost. The some other parallel adder/subtraction and adder designs are explored (Rekha James et al, 27; Himanshuthapliyalet al, 27; Majid Mohammadiet al, 28 and H. G. Rangarajuet al, 2). Thus, from a careful review of the previous work on reversible adder and carry skip adder design, no such designs in Q framework. 3. Proposed esign of Reversible cd dder this section, we design a compact circuit of reversible adder. To design a compact adder, we propose three new type of reversible gates in Subsection 3.. approach to less architectural complexity, we design FS cell and F_F_H cell in subsection of design of parallel adder and design of carry skip adder.these designs are then extensively utilized to design -digit and n-digit adder.

288 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 3. Three Proposed Reversible s: Three new types of reversible gates are proposed which are helpful for the design of reversible adder and carry skip adder circuit. The first is the 3x3 HS gate. Fig. 2a, 2b depicted the block diagram and quantum implementation of the HS gate. The HS gate has a quantum cost and hardware complexity are 5 and 3α+2β+δ respectively. It consist of four XOR gates, two controlled-v and one controlled-v + gate. The truth table of this 3x3 HS gate is shown in Table.The proposed HS gate, can implement the operation of half adder and half subtraction, depicted in Fig. 2c. (a) HS P Q R (b) (c) HS Sum arry HS ifference orrow Fig. 2: Proposedreversible HS gate (a) lock diagram (b) Quantum implementation. (c) HS gate implement as half adder and half subtraction. Table : Reversibility of the proposed HS gate. INPUT OUTPUT P Q R The second new type of 4x4 proposed gate is the FS gate. Fig. 3a, 3b depicted the block diagram and quantum implementation of the FS gate. The FS gate has a quantum cost and hardware complexity are 8 and 8α+2β respectively. It consist of six XOR gates, two controlled-v and one controlled-v + gate. The truth table of this 4x4 FS gate is shown in Table 2.The proposed FS gate, can perform the operation of full adder and full subtraction, depicted in Fig. 3c.

289 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 (a) FS P Q ( ) ( ) R S ( ) ( ) ( ) ( ) (b) Sum FS arry ( ) R S (c) FS iff orr ( ) R S (d) FS P Q R S FS P Q R S Fig. 3: Proposed reversible FS gate (a) lock diagram (b) Quantum implementation (c) FS gate implement as full adder and full subtraction (d) FS gate implement as XOR, N, XNOR, OR and verter. Table 2: Reversibility of the proposed FS gate. INPUT OUTPUT P Q R S The third new type of 5x5 proposed gate is the O gate, which produce outputs P ( ), Q, R, S and T ( ) E. Fig. 4a, 4b depicted the block diagram and quantum implementation of the O gate. The O gate has a quantum cost and hardware complexity are and 4α+2β respectively. It consist of seven XOR gates, four controlled-v and two controlled-v + gate. The truth table of this 4x4 O gate is shown in Table 3.When the first input is set to, and other four inputs are set to S, S2,

29 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 and E 3 the O gate simultaneously realizes Q S, R S2, S S3 and T S3(S S2 ) 3, the logic expression is used for overflow detection, depicted in Fig. 4c. E (a) E (b) S 3 O O P ( ) Q R S T ( ) E ( ) ( ) E S S3(S S2) 3 E ( ) ( ) E (c) Fig. 4: Proposed reversible O gate (a) lock diagram (b) Quantum implementation (c) lock diagram of overflow detection Table 3: Reversibility of the proposed O gate. INPUT OUTPUT E P Q R S T

29 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 3.2 esign of Parallel adder reversible design, the FS gate can be used as the full adder module. Therefore, 4-bit parallel adder we use four FS gates is depicted in Fig. 5. The quantum cost of single FS gate is 8.Therefore, the quantum cost of 4-bit parallel adder is 32. Q (4-bit parallel adder) = 4Q (FS gate) = 4x8 = 32. 2 4 4 2 3 3 2 in 4 4 3 3 2 2 FS FS FS FS FS ell in S S S 3 3 3 2 3 S S Fig. 5: lock diagram of 4-bit reversible parallel adder. S S 3.3 esign of Overflow etection and orrection ircuits: this section, we propose a new type of overflow detection and correction circuit. lemmas is offered for circuit design. Lemma-: addition, the overflow detection circuit can be realized by at least one reversible O gate. Proof: number overflow occurs if the final obtained result is greater than 9 (). FS cell, the carry-out shown by 3 and it is fixed by the FS cell,depicted in Fig 3c. For overflow detection carryout ( 3 ) is applied to O and also other inputs its enable the overflow detection circuit and generate logic bit expression out (S S2)S3 3.If out =, nothing is required for addition and another case out =, binary (6) should be added to the sum. overflow detection circuit utilize only one O gate, depicted in Fig. 4c. Lemma-2: reversible adder circuit, overflow correction logic can be realized by at least three reversible gates with 5 quantum cost. Proof: n overflow correction required when out is and no correction required when out is. When out = required to add of (6). this circuit, we use one FG as a sum logic, one FS gate implement as a full adder and one HS gate as half adder. The proposed overflow correction is depicted in Fig. 6. The Q of FG, FS and HS gate are, 8 and 5, respectively; therefore the Q of the circuit is 4. Q (ircuit of overflow detection) =Q (FG)+ Q (FS)+ Q (HS)=+8+5=4 S 3 out2 S out S out FG FS HS F_F_H ell ~ 2 Fig. 6: lock diagram of overflow correction. out out Z3 2 Z Z out 2 3 out Z 2 Z Z 3.4 esign of adder using proposed gates: design of -digit adder has three levels: First level is parallel adder (Used as FS cell), second as overflow detection (Used as O gate), and the third is the overflow correction (Used as F_F_H cell), depicted in Fig. 7a.

292 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 2 2 3 3 4 4 FS ell S 3 O S out F_F_H ell Z Z Z 2 out Z 3 Fig. 7a: esign of -digit adder. First level: 4-bit parallel adder operation uses an FS cell, initially set in = and added a bit ( 4 4, 3 3, 2 2, ) and generate output marked as (,,S,S ) and the final carry output marked as 3 Second level: Overflow occurs when the output logic is greater than 9 () and the out is set by the O gate by using logic expression out (S S2)S3 3.Overflow detection design utilizes only one reversible O gate. Third level: overflow correction utilize F_F_H ell. The new type of -digit adder is depicted in Fig. 7a. It has 8 gate count, garbage outputs and 7 constant inputs. Quantum cost of FS cell, O gate and F_F_H cell are 32, and 4, respectively; therefore, the quantum cost of -digit adder is Q (-digit adder) = Q (FS cell) + Q (O gate) + Q (F_F_H cell)= 32++4= 56 Fig. 7b depicted the circuit of n-digit adder which is designed by cascading of -digit adder. P 4 P 3 P 3 P P P P P P FS ell S P S P SP S P P O SP S P out F_F_H ell Z' P Z P ZP out ZP FG q 4 Z ' q q 3 q 3 q q q q FS ell S q Sq S q S q O S q S q F_F_H ell Z q Zq out q q q out Zq Fig. 7b: esign of n-digit adder. 3.5 esign of arry Skip adder using proposed gate: The design of carry skip -digit adder uses four levels. Fig. 9 depicts the carry skip -digit adder design. First level indicates the design operation performed by FS carry skip cell (Fig. 8). The quantum cost of single FS gate is 8.Therefore, the quantum cost of FS carry skip cell is 32. Q (FS carry skip cell) = 4Q (FS gate) = 4x8 = 32. Second level indicates the design of arry Skip logic, which consists of four gates of two types (3 HS gate + FRG gate).the carry bit named (Y) is found by preparation of propagation logic P = (P P 2 P 3 P 4 ) where Pi i i i.e Y Pin P 4 for analyzing this expression set P= then the carry 4 propagates like in parallel adder else case in propagate for carry skip logic. The generation of 4 will take time. FRG will hold for a generation of the carry bit (Y) until 4 is solved. Third level: esign operation performed by O gate. Fourth level: esign operation performed by overflow correction by using F_F_H cell.

293 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 4 4 3 3 2 2 in 4 4 3 3 2 2 FS FS FS FS FS arry skip ell S 4 4 4 S 4 R 3 3 Q P S 4 S 4 S R Q P S Fig. 8: lock diagram of FS carry skip cell. 4 4 3 3 2 2 in FS arry skip ell FG 4 S S 4 R Q P S HS HS HS X FRG Y O out S 4 F_F_H ell Z 4 Z 3 out Z 2 Z Fig. 9: Proposed design of arry Skip -digit adder. The new type of carry skip adder is depicted in Fig. 9. It has 3 gate count, 5 garbage output and constant input. Quantum cost of FS cell, HS, FG, FRG, O and F_F_H cell are 32, 5,, 5, and 4, respectively; therefore, the quantum cost of -carry skip adder is Q (-digit carry skip adder) = Q (FS cell) + 3Q (HS) + Q (FG) + Q (FRG) + Q (O gate) + Q (F_F_H cell) = x32+3x5++ x5+x+x4= 77.

294 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 lgorithm. I. arry Skip -digit adder. Select 4-bit arguments ( 4, 4, 3, 3, 2, 2,, ), carry in ( in ) and generate outputs as ( out, Z 4, Z 3, Z 2, Z ).egin Level 2.For (i = to 4) { 3. Pi i i // Propagate bit (P i ) is generated from FS carry skip cell. } 4.P = (P P 2 P 3 P 4 ) // Generate P from each HS gate. Level 2 5.Find Si (i i i ) // Sum from FS carry skip cell. 6. arry = {( i i)i ii} // arry from FS carry skip cell. Level 3 7.Find Y Xin Xout // Generate Y from FRG gate. Level 4 8. Find out {S 4(S2 S3) Y} // Generate out from O. Level 5 9.Find out > (9) // Overflow condition occur then add and use F_F_H ell for correction logic. Level 6. Record each output ( out, Z 4, Z 3, Z 2, Z ). End; 4. Qca Implementation of Od : We designed the Q layout structure of the O gate is depicted in Fig. that is composed of 74 cells and one layer. Five of these, acting as inputs to the cell, are marked,,, and E. The layout of the O gate show that there is the minimum cell used with minimum area. The Q layout of O gate performs the oolean expression P ( ), Q=, R=, S= and T ( ) E RESULT N ISUSSION The design of O gate is simulated to test the workability with Qesigner version of 2..3 and follow the truth table of this gate, depicted in Fig 2.We simulate O gate by using bistable approximation with default parameters. addition, the overflow detection operation performed by O gate. The O gate capability of performing overflow detection condition by fixing input =; and other four inputs (S ), ( ), ( ) and E ( 3 ) are for four bits to be added the O gate simultaneously implements Q (S ), R ( ), S ( ) and T ( out ).Fig. 3 reveals that when the input = and S =, then the output becomes out =, when the input = and =,then the output becomes out = andwhen 3 =, then output become out =. a similar way whenoutput( out =) signifies correction required. other case out = means no correction required.from Fig.2 and 3, we can see that polarization value of all four output signals is fairly better. P 2 3 2 means lock to lock3 Maj 3 2 2 3 E 2 3 2 T 2 3 Q R Fig. : Q block diagram of O gate with clock zone.

295 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 Fig. : Q layout of O gate. Fig. 2: Simulation result of O.

296 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 Fig. 3: Simulation result of overflow detection by using O gate. Table 4: omparison of overflow detection. Methods NOG I U Quantum ost Proposed design (O gate) Hasan abu et al. 26 James et al. 27 shiskumar iswas et al. 28 Haghparast et al. 28 Rigui Zhou et al. 22.27 ircuit area in (µm 2 ) 3 6 3 3 5 Not mentioned 2 4 2 22 Not mentioned 3 3 5 Not mentioned 3 6 3 27 Not mentioned 9 Not mentioned Table 5: omparison between Proposed and existing design of adder in terms of evaluation parameters. Methods -digit adder NOG I U Q Proposed work 8 7 8 56 Hasan abu et al. 26 23 22 9 2 39 James et al. 27 9 8 9 44 shiskumar iswas et al. 28 7 55 Haghparast et al. 28 4 22 9 3 79 Rigui Zhou et al. 22 8 7 8 54 Table 6: omparison between proposed and existing design of carry skip adder in terms of evaluation parameters Methods -digit arry skip adder NOG I U Q Proposed work 3 5 3 77 HimanshuThapliyal et al. 26 2 27 2 43 shiskumar iswas et al. 28 5 4 2 7

297 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 Table 7: Q, Overflow detection behaviour analysis by using O gate ell Total area Reversible O gate No. of MV s used complexity (nm 2 ell area (nm 2 ) rea usage (%) ) Proposed design 5 Majority+3 verter 74 27,5455 56,376 2.466 onclusion: this paper, a new and improved type of reversible adder and carry skip adder are presented. The proposed circuits is demonstrated around the Q technology in terms of low clock cycle delay, high device density, high computing speed and no loss of power in signal transition and propagation. addition, we have proposed three new reversible gates named as HS gate, FS gate and O gate to optimize adder circuit. The new FS gate can be utilized as a reversible full adder with using only one gate count and eight quantum cost. The O gate layout verifying the Qesigner frameworkand the simulation result found to ensures the correctness of the design. uring the Q layout design of O gate we take care of minimizing the cells, clock cycle delay, total area and cell area which is found to be 74, 3, 27,5455nm 2 and 56,376nm 2 respectively. We have established the optimal parameter with several definitions and lemmas for adder circuit design. Hence we conclude that the newreversible gates, adder and carry skip adder will be absolutely useful in low power digital computing circuits, arithmetic and logic unit, low power nanotechnology era and quantum computer. REFERENES shis Kumar iswas et al, 28. Efficient approaches for designing reversible binary coded decimal adders. Microelectronics journal, 39(2): 693-73. Rekha, K. James et al, 27. new look at reversible logic implementation of decimal adder, IEEE symposium on System-on-hip: -4. Rolf. Landauer, 96. Irreversibility and heat generation in the computing process. IM journal of research and development, 5(3): 83-9. harles H. ennett, 973. Logical reversibility of computation, IM journal of Research and evelopment, 7(6): 525-532. Krishnaveni,., and M. Priya. Geetha, 2. novel design of reversible serial and parallel adder/subtractor, ternational Journal of Engineering Science and Technology, 3(3). Rangaraju, H.G., U. Venugopal, K.N. Muralidhara, and K.. Raja, 2. Low power reversible parallel binary adder/subtractor, ternational Journal of VLSI esign & ommunication Systems, pp: -2. Majid Mohammadi et al, 28. esign and optimization of reversible bcd adder/subtractor circuit for quantum and nanotechnology based systems, World pplied Sciences Journal, 4(6): 787-792. HimanshuThapliyal et al, 26. Novel adders and their reversible logic implementation, IEEEternational onference on Embedded Systems and esign, pp: -6. Haghparast, Majid, and KeivanNavi, 28. novel reversible adder for nanotechnology based systems, merican Journal of pplied Sciences, 5(3): 282-288. Rangaraju, H.G., U. Venugopal, K.N. Muralidhara, and K.. Raja, 2. esign of Efficient Reversible Parallel inary dder/subtractor, Springer erlin Heidelberg in omputer Networks and formation Technologies, pp: 83-87. HimanshuThapliyal, et al, 27. Partial reversible gates (PRG) for reversible arithmetic,ternational onference on omputer esign (ES 7), Las Vegas, U.S.: 8-9. abu, Hafiz Md Hasan, and hsan Raja howdhury, 26. esign of a compact reversible binary coded decimal adder circuit, Journal of Systems rchitecture, 52(5): 272-282. Yang, Guowu, Xiaoyu Song, William NN Hung, and Marek Perkowski, 25. i-direction synthesis for reversible circuits, IEEE omputer Society nnual Symposium on VLSI: 4-9. iswas, shiskumer, MdMahmudul Hasan, Moshaddek Hasan, hsan Raja howdhury, and Hafiz Md Hasan abu, 28. novel approach to design adder and arry Skip adder. IEEE onference on VLSI esign, pp: 566-57. Zhou, Rigui, Manqun Zhang, Qian Wu, and Yang Shi, 22. esigning novel reversible adder and parallel adder/subtraction using new reversible logic gates, ternational Journal of Electronics, 99(): 395-44. Misra. N.K., Kushwaha. Mukesh. K, S. Wairya, mit Kumar, 25. Feasible Methodology for optimization of a novel reversible binary compressor, ternational Journal of VLSI design & ommunication Systems, 6(4): -3. Thapliyal, Himanshu and M.. Srinivas, 25. novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures, Springer erlin Heidelberg on dvances in omputer Systems rchitecture, pp: 85-87. ngizi, Shaahin, Esamlkaldy, Nader agherzadeh, and Keivan Navi, 24. Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. Journal of Low Power Electronics, (2): 259-27. Misra, N.K., S. Wairya, V.K. Singh, 25. pproaches to esign Feasible Error ontrol Scheme ased on Reversible Series s, European Journal of Scientific Research, 29(3):

298 Neeraj Kumar Misra et al, 25 ustralian Journal of asic and pplied Sciences, 9(3) September 25, Pages: 286-298 224-24. Mustafa, M., and M.R. eigh, 23. esign and implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count, dian Journal of Pure and pplied Physics, 5(): 6-66. ibhash Sen et al, 25. Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. omputers & Electrical Engineering, 45: 42-54. ibhas Sen et al, 23. Reversible logic-based fault-tolerant nanocircuits in Q. ISRN Electronics. Misra, N.K., Kushwaha, Mukesh, K, S. Wairya, mit Kumar, 25. Efficient esign of Reversibledder ircuits for Low Power pplications, ternational Journal of omputer pplications, 7(9): 37-45. ahar, li Newaz, Sajjad Waheed, and Nazir Hossain, 25. new approach of presenting reversible logic gate in nanoscale.springerplus, 4(): 53.