Chapter 2 Fault Modeling Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jungli, Taiwan
Outline Why Model Faults? Fault Models (Faults) Test, Test Set, and Testing Fault Collapsing & Test Compaction Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Test Process The testing problem Given a set of faults in the circuit under test (or device under test), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage? Test process What faults to test? (fault modeling) How are test pattern obtained? (test pattern generation) How is test quality (fault coverage) measured? (fault simulation)? How are test vectors applied and results evaluated? (ATE/BIST) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
Defect Categories Defect categories Random defects, which are independent of designs and processes Systematic defects, which depend on designs and processes used for manufacturing For example, random defects might be caused by random particles scattered on a wafer during manufacturing Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Logical Fault Models Systematic defects might be caused by process variations, signal integrity, and design integrity issues It is possible both random and systematic defects could happen on a single die With the continuous shrinking of feature sizes, somewhere below the 180nm technology node, system defects have a larger impact on yield than random defects Logical faults Logical faults represent the physical defects on the behaviors of the systems Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Why Model Faults I/O function tests inadequate for manufacturing (functionality versus component and interconnection testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
Fault Nature Logical fault One that causes the logic function of a circuit element to be changed to some other function Parametric fault One that alters the magnitude of a circuit parameter, causing a change in some factor such as resistance, capacitance, current, etc. Delay fault One that relates to circuit delays such as slow gates, usually affecting the timing of the circuit, which may cause hazards, or performance degradation, etc. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
Fault Duration Permanent fault A lasting fault that is continuous and stable, whose nature does not change before, during, and after testing. E.g., a broken wire, an incorrect bonding, etc. A.k.a hard fault or solid fault Temporary fault A fault that is present only part of the time, occurring at random moments and affecting the system for finite, but unknown, intervals of time Transition fault Caused by environmental conditions, e.g., cosmic rays, alphaparticle, etc. A.k.a. soft error in RAMs Intermittent fault Caused by non-enviornmental conditions, e.g., marginal values of component parameters, wear-out, or critical timing Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Single Stuck-At Fault Single (line) stuck-at fault The given line has a constant value (0/1) independent of other signal values in the circuit Properties Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Simple logical model is independent of technology details It reduces the complexity of fault-detection algorithms One stuck-at fault can model more than one kind of defect Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
Single Stuck-At Fault Example A circuit with single stuck-at fault 1 1 1 0 s/1 0 (1) POWER IN Output Shorted to 1 OUT GROUND Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
Number of Single Stuck-At Faults Number of fault sites in a Boolean gate circuit #PI + #gates + #(fanout branches) Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults 1 0 a b c d e f s/0 g 1 h i Faulty circuit value Good circuit value j 0(1) 1(0) z k 1 Test pattern (vector) for h s/0 fault Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Multiple Stuck-At Faults Multiple stuck-at fault Several single stuck-at faults occur at the same time Multiple stuck-at faults are usually not considered in practice because of two reasons The number of multiple stuck-at faults in a circuit with k lines is 3 K -1, which is too large a number even for circuits of moderate size Tests for single stuck-at faults are known to cover a very high percentage (greater than 99.6%) of multiple stuck-at faults when the circuit is large and has several outputs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
Bridging Faults Bridging fault Two or more normally distinct points (lines) are shorted together Two types of bridging faults Input bridging Can form wired logic or voting model Feedback (input-to-output) bridging Can introduce feedback Can cause oscillation or latching (additional memory) Input bridging feedback bridging x 1 x 1 x x 2 x 2 F y F y 1 x 2 F y x n x n Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 x n
Bridging Faults A S source B S A D destination B D bridging fault A S A D A S A D A S A D A S A D B S B D B S B D B S B D B S B D Wired-AND Wired-OR A dominates B B dominates A A S A D A S A D A S A D A S A D B S B D B S B D B S B D B S B D A dominate-and B A dominate-or B B dominate-and A B dominate-or A Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU
Pattern-Sensitive Faults Pattern-sensitive fault The presence of a faulty signal depends on signal values of nearby points Most common in DRAM (dynamic random access memory) 0 0 0 0 0 0 0 0 0 a b 0 0 0 c 0 a=b=0, c=0 a=b=1, c=1 Coupling fault Pattern sensitivity between a pair of cells Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
Single Cell Fault Cells can have any implementation All possible (combinational) cell faults are allowed; truth table can change in any way C-testability: constant number of test patterns, independent of circuit size (Ripple-carry adder needs only 8 test patterns for all single stuckat faults) x 1 y 1 x 2 y 2 x 3 y 3 x 4 y 4 c 0 FA FA FA FA c 4 z 1 z 2 z 3 z 4 Source: K. Chakrabarty Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
Transistor Faults MOS transistor is considered an ideal switch and two types of faults are modeled Stuck-open -- a single transistor is permanently stuck in the open state Turn the circuit into a sequential one Need a sequence of at least 2 tests to detect a single fault Unique to CMOS circuits Stuck-on -- a single transistor is permanently shorted irrespective of its gate voltage Detection of a stuck-open fault requires two vectors Detection of a stuck-on fault requires the measurement of quiescent current (I DDQ ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Transistor Stuck-Open Fault Example: 1 0 0 0 A B pmos V DD Stuck-open C Vector 1: test for A s/0 (Initialization vector) Vector 2 (test for A s/1) Two-vector stuck-open test can be constructed by ordering two stuck-at tests 0 1(Z) nmos Good circuit states Faulty circuit states Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Test Stuck-On Fault Using I DDQ Example: Test vector for A s/0 1 A pmos V DD Stuck-on I DDQ path in faulty circuit 0 B C 0 (X) Good circuit state nmos Faulty circuit state Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
I DDQ Test in Nano-scale Era Major problem: may result in unacceptable yield loss Mean of fault-free current Mean of faulty current Density I DDQ density function Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
Crosspoint Fault A PLA has a device (diode or transistor) at every crosspoint in the AND and OR arrays. The connection of each transistor is programmed to realize the desired logic A crosspoint fault can be caused by an extra or a missing device X 1 X 1 X 2 X 2 AND array Z x x 1 2 Z x 1 x2 x2 Z=X 1 X 2 +X 1 X 2 OR array Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
Delay Fault Delay fault Propagation delays along a path (gate) fall outside the desired limits. Two types of delay faults: path delay fault or gate delay fault Example: 0 0 1 0 X 1 X 2 Z=X 1 X 2 +X 2 X 3 1 1 X 3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
Transition Delay Fault Transition delay fault A gate output may be slow-to-rise or slow-to-fall and that this time is longer than a predefined level If the delay fault is large enough, the transition delay fault behaves as a SAF and can be modeled using that method The primary weakness of transition delay fault Two pattern sequences for initialization and transition detection are needed The minimum achievable delay fault size is difficult to determine because of timing hazards. Consequently, a whole mission clock cycle is usually used Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
Crosstalk Defects Wire aspect scaling with technology [Source: S.-T. Zachariah, DATE03] Capacitive crosstalk noise results from parasitic coupling between two signal nets Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
Maximal Aggressor Fault Model Y 1 Y 1 Y 1 Y 1 Y i-1 Y i Y i+1 Y N 0 Victim Y i-1 Y i Y i+1 Y N 1 Victim Y i-1 Y i Y i+1 Y N Victim Y i-1 Y i Y i+1 Y N Victim Victim Victim Victim Victim Positive glitch Negative glitch Slow to fall Slow to rise Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
Test & Test Set A test for a fault in a circuit C is an input combination for which the output(s) of C is different when is present than when it is not. A.k.a. test pattern or test vector X detect then f ( X ) f ( X ) 1 A test set for a class of faults A is a set of tests T such that A, t T and t detects The test set for a fault is T f f For example, X 1 X 2 X 3 X 4 s/0 f=x 1 X 2 +X 3 X 4 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26 T ( X X 1 1 f X X 3 2 X 4 {0011,0111,1011} f X 3 X X 2 4 ) X X 3 X 4 1 X 2
Testing & Diagnosis Testing is a process which includes test pattern generation, test pattern application, and output evaluation. Fault detection tells whether a circuit is fault-free or not Fault location provides the location of the detected fault Fault diagnosis provides the location and the type of the detected fault The input X distinguishes a fault from another fault iff f ( X ) f ( X ), i.e., f ( X ) f ( X ) 1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
Testing & Diagnosis Example: a b c a b c 0 0 0 0 1 1 1 0 1 1 1 1 c a/0 0 1 0 1 c a/1 c b/0 c b/1 c c/0 c c/1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 C a/0 and C c/0 are detected by the test pattern (1,0) If we apply two test patterns: (1,0) & (0, 1) Two corresponding outputs are faultyc c/0 Only the output with respect to the input (1,0) is faultyc a/0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
Fault Collapsing To generate tests for digital circuits, the test tools are provided with a circuit description, a netlist. The tool then creates a list of all faults (fault list) to be detected For large circuits, the list can be quite long. It is thus beneficial to minimize the list whenever possible Some faults may be detected by the same test patterns. Therefore, only one of these faults needs to be included in the fault list Fault collapsing can reduce the size of fault list with two concepts: equivalence and dominance Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
Equivalent Fault Collapsing Definition Two faults are called equivalent if every pattern that detects one of the faults also detects the other. That is, their test sets, T 1 and T 2, are identical: and Example: A B Summary C Original fault list={a/0, A/1, B/0, B/1, C/0, C/1} But A/0, B/0, and C/0 are equivalent Therefore, reduced fault list= {A/1, B/1, C/1, (C/0 or A/0 or B/0)} AND gate: all s/0 faults are equivalent OR gate: all s/1 faults are equivalent For an n-input gate, only n+2 faults need to be considered with equivalence fault collapsing Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
Dominance Fault Collapsing Definition A fault, f 1, dominates another fault, f 2, if the test set of the latter, T 2, is a subset of the test set of the former, T 1 ; that is, T2 T 1. Any test pattern that detects f 2 will also detect f 1. Therefore, f 2 implies f 1 and it is sufficient to include f 2 in the fault list Consider a two-input (A and B) AND gate, a test pattern for the S/1 fault on any of the inputs detects S/1 fault on the output (C). Then C/1 can be dropped from the fault list. Therefore, the fault list is reduced to {A/0,A/1,B/1} Summary l n1 /1 l n1 /0 For an n-input AND gate, dominates For an n-input OR gate, dominates l i /1, i l i /0, i Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
Collapsing by Fault Diagrams Represent each line x by a pair of circles: the upper circle stands for x/1, and the lower circle for x/0 Two circles are connected by an edge if they are equivalent Each net on the diagram represents a single fault equivalence class a b & c a/1 a/0 b/1 b/0 c/1 c/0 {a/0,b/0,c/1} {a/1} {b/1} {c/0} Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
Collapsing by Fault Diagrams Fault equivalent diagrams for primitive logic gates AND OR NOR NOT For example a c e I b & d & f a b c d f 6 equivalent classes (6 tests) e Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
Collapsing by Fault Diagrams Add directed arcs from the dominating faults toward the dominated faults AND OR NAND NOR For fanouts, view the stem and branch as a separate line. Direction of dominance is opposite that of the gates Equivalence network Two tests Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
Example a b c d e & & f g h 16 single faults 10 equivalent classes 6 tests a f b d h e g c Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
Test Compaction Equivalence fault collapsing + dominance fault collapsing Only n+1 faults on any n-input gate need be considered Definition Test compaction refers to the process of reducing the number of test patterns in a test set without reducing its fault coverage Equivalence fault collapsing and dominance fault collapsing can be used to aid test compaction Theorem In a fanout-free combinational circuit, any test set which detects all stuck faults on primary inputs will detect all stuck at faults Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
Test Compaction Definition The set of all primary inputs and all fanout branches are called checkpoints of the circuit Example, stem branches Primary inputs Primary outputs Theorem In a combinational circuit, any test set which detects all single (multiple) stuck faults on checkpoints will detect all single (multiple) stuck faults. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37
Fault Masking Let T X be the test that detects a fault X. We say that a fault Y functionally masks the fault X iff the multiple fault {Y, G} is not detected by any test in T X E.g., as the following figure shows, the test 011 is the only test that detects the fault c/0. The same test does not detect the multiple fault {c/0, a/1}. Thus a/1 masks c/0 a b c 0 1 1/0 & & 1 0 & 0/1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38
Summary Basic fault models Single stuck-at fault Bridging fault Pattern-sensitive fault Delay fault Fault modeling can simplify the complexity of testing Test compaction is usually used to reduce the number of test patterns Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39