ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]
Dynamic CMOS l In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fan-in of N requires 2N devices l Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires only N + 2 transistors takes a sequence of precharge and conditional evaluation phases to realize logic functions ΗΜΥ307 Δ11 Dynamic CMOS Circuits.2 Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Gate M p Out M p off on 1 Out!((A&B) C) In 1 In 2 In 3 PDN C L A B C M e M e off on Two phase operation Precharge ( = 0) Evaluate ( = 1) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.4 Θεοχαρίδης, ΗΜΥ, 2018
Conditions on Output l Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. l Inputs to the gate can make at most one transition during evaluation. l Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L ΗΜΥ307 Δ11 Dynamic CMOS Circuits.5 Θεοχαρίδης, ΗΜΥ, 2018
Properties of Dynamic Gates l Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS l Full swing outputs (V OL = GND and V OH = V DD ) l Nonratioed - sizing of the devices is not important for proper functioning (only for performance) l Faster switching speeds reduced load capacitance due to lower number of transistors per gate (C int ) so a reduced logical effort reduced load capacitance due to smaller fan-out (C ext ) no I sc, so all the current provided by PDN goes into discharging C L Ignoring the influence of precharge time on the switching speed of the gate, t plh = 0 but the presence of the evaluation transistor slows down the t phl ΗΜΥ307 Δ11 Dynamic CMOS Circuits.6 Θεοχαρίδης, ΗΜΥ, 2018
Properties of Dynamic Gates, con t l Power dissipation should be better consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating lower C L - both C int (since there are fewer transistors connected to the drain output) and C ext (since there the output load is one per connected gate, not two) by construction can have at most one transition per cycle no glitching l But power dissipation can be significantly higher due to higher transition probabilities extra load on l PDN starts to work as soon as the input signals exceed V Tn, so set V M, V IH and V IL all equal to V Tn low noise margin (NM L ) l Needs a precharge clock ΗΜΥ307 Δ11 Dynamic CMOS Circuits.7 Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Behavior Out 2.5 Evaluate In 1 In 2 Voltage 1.5 In 3 In 4 0.5-0.5 In & Out 0 0.5 1 Time, ns Precharge #Trns V OH V OL V M NM H NM L t phl t plh t p 6 2.5V 0V V Tn 2.5-V Tn V Tn 110ps 0ns 83ps ΗΜΥ307 Δ11 Dynamic CMOS Circuits.8 Θεοχαρίδης, ΗΜΥ, 2018
Gate Parameters are Time Independent l The amount by which the output voltage drops is a strong function of the input voltage and the available evaluation time. Noise needed to corrupt the signal has to be larger if the evaluation time is short i.e., the switching threshold is truly time independent. Voltage (V) 2.5 1.5 0.5 V out (V G =0.45) V out (V G =0.55) Vout (V G =0.5) V G -0.5 0 20 40 60 80 100 Time (ns) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.9 Θεοχαρίδης, ΗΜΥ, 2018
Power Consumption of Dynamic Gate M p Out In 1 In 2 In 3 PDN M e C L Power only dissipated when previous Out = 0 ΗΜΥ307 Δ11 Dynamic CMOS Circuits.10 Θεοχαρίδης, ΗΜΥ, 2018
Dynamic Power Consumption is Data Dependent A B Out 0 0 1 0 1 0 1 0 0 1 1 0 Dynamic 2-input NOR Gate Assume signal probabilities P A=1 = 1/2 P B=1 = 1/2 Then transition probability P 0 1 = P out=0 x P out=1 = 3/4 x 1 = 3/4 Switching activity can be higher in dynamic gates! P 0 1 = P out=0 ΗΜΥ307 Δ11 Dynamic CMOS Circuits.11 Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 1: Charge Leakage A=0 M p M e 4 2 1 3 C L Out V Out Evaluate Precharge Leakage sources Minimum clock rate of a few khz ΗΜΥ307 Δ11 Dynamic CMOS Circuits.12 Θεοχαρίδης, ΗΜΥ, 2018
Impact of Charge Leakage l Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. 2.5 Voltage (V) 1.5 0.5 Out -0.5 0 20 40 Time (ms) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.13 Θεοχαρίδης, ΗΜΥ, 2018
A Solution to Charge Leakage q Keeper compensates for the charge lost due to the pulldown leakage paths. Keeper M p M kp A B C L!Out M e Same approach as level restorer for pass transistor logic ΗΜΥ307 Δ11 Dynamic CMOS Circuits.14 Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 2: Charge Sharing A B=0 M p M e C a C b C L Out Charge stored originally on C L is redistributed (shared) over C L and C A leading to static power consumption by downstream gates and possible circuit malfunction. When DV out = - V DD (C a / (C a + C L )) the drop in V out is large enough to be below the switching threshold of the gate it drives causing a malfunction. ΗΜΥ307 Δ11 Dynamic CMOS Circuits.15 Θεοχαρίδης, ΗΜΥ, 2018
Charge Sharing Example What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.) y = A Å B Å C Load inverter a A!A C y =50fF C a =15fF B b!b B!B c d C b =15fF C c =15fF!C C C d =10fF DV out = - V DD ((C a + C c )/((C a + C c ) + C y )) = - 2.5V*(30/(30+50)) = -0.94V ΗΜΥ307 Δ11 Dynamic CMOS Circuits.17 Θεοχαρίδης, ΗΜΥ, 2018
Solution to Charge Redistribution A M p M kp Out B M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.18 Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 3: Backgate Coupling q Susceptible to crosstalk due to 1) high impedance of the output node and 2) capacitive coupling Out2 capacitively couples with Out1 through the gate-source and gate-drain capacitances of M4 M p Out1 =1 M 6 M 5 Out2 =0 A=0 M 1 C L1 M 4 C L2 B=0 M 2 M 3 M e In Dynamic NAND Static NAND ΗΜΥ307 Δ11 Dynamic CMOS Circuits.19 Θεοχαρίδης, ΗΜΥ, 2018
Backgate Coupling Effect q Capacitive coupling means Out1 drops significantly so Out2 doesn t go all the way to ground 3 Voltage 2 1 Out1 0 In Out2-1 0 2 Time, ns 4 6 ΗΜΥ307 Δ11 Dynamic CMOS Circuits.20 Θεοχαρίδης, ΗΜΥ, 2018
Issues in Dynamic Design 4: Clock Feedthrough q A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node A B M p M e C L Out Coupling between Out and input of the precharge device due to the gatedrain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out. ΗΜΥ307 Δ11 Dynamic CMOS Circuits.21 Θεοχαρίδης, ΗΜΥ, 2018
Clock Feedthrough In 1 Out 2.5 Clock feedthrough In 2 1.5 In 3 In 4 Voltage 0.5 In & Out -0.5 0 0.5 Time, ns 1 Clock feedthrough ΗΜΥ307 Δ11 Dynamic CMOS Circuits.22 Θεοχαρίδης, ΗΜΥ, 2018
Cascading Dynamic Gates V M p Out1 M p Out2 In In M e M e Out1 Out2 V Tn DV t Only a single 0 1 transition allowed at the inputs during the evaluation period! ΗΜΥ307 Δ11 Dynamic CMOS Circuits.23 Θεοχαρίδης, ΗΜΥ, 2018
Domino Logic In 1 In 2 M p PDN 1 1 1 0 Out1 0 0 0 1 In 4 M p M kp PDN Out2 In 3 In 5 M e M e ΗΜΥ307 Δ11 Dynamic CMOS Circuits.24 Θεοχαρίδης, ΗΜΥ, 2018
Why Domino? In 1 In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! ΗΜΥ307 Δ11 Dynamic CMOS Circuits.25 Θεοχαρίδης, ΗΜΥ, 2018
Domino Manchester Carry Chain 3 3 3 3 3 P 0 P 1 P 2 P 3 4 C i,0 5 G 0 4 3 2 1 C i,4 G 1 3 G 2 2 G 3 1 6 5 4 3 2!(G 0 + P 0 C i,0 )!(G 1 + P 1 G 0 + P 1 P 0 C i,0 ) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.27 Θεοχαρίδης, ΗΜΥ, 2018
Domino Comparator A3 A2 A1 A0 Out B3 B2 B1 B0 ΗΜΥ307 Δ11 Dynamic CMOS Circuits.29 Θεοχαρίδης, ΗΜΥ, 2018
Properties of Domino Logic l Only non-inverting logic can be implemented, fixes include can reorganize the logic using Boolean transformations use differential logic (dual rail) use np-cmos (zipper) l Very high speed t phl = 0 static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances) ΗΜΥ307 Δ11 Dynamic CMOS Circuits.30 Θεοχαρίδης, ΗΜΥ, 2018
Differential (Dual Rail) Domino Out = AB off on M p M kp M kp M p 1 0 1 0 A B!A!B!Out =!(AB) M e Due to its high-performance, differential domino is very popular and is used in several commercial microprocessors! ΗΜΥ307 Δ11 Dynamic CMOS Circuits.31 Θεοχαρίδης, ΗΜΥ, 2018
np-cmos (Zipper) In 1 M p 1 1 1 0 Out1! In 4 M e PUN In 2 In 3 PDN M e In 5! M p 0 0 0 1 Out2 (to PDN) to other PDN s to other PUN s Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN ΗΜΥ307 Δ11 Dynamic CMOS Circuits.32 Θεοχαρίδης, ΗΜΥ, 2018
np-cmos Adder Circuit!A 1!B 1!B 1!C 1!A!A1!A 1 1!B 1!C 1!B 1 1 x!! 0 x C 2 0 x 1 x Sum 1 C 0 0 x!c 1 A 0 B 0 C 0 A 0 A 0 B 0 C 0 A 0 B 0 1 x 1 x!! B 0 0 x!sum 0 ΗΜΥ307 Δ11 Dynamic CMOS Circuits.33 Θεοχαρίδης, ΗΜΥ, 2018
DCVS Logic 1 0 on off off on 0 1 Out!Out In 1!In 1 In 2!In 2 PDN1 off on PDN2 on off PDN1 and PDN2 are mutually exclusive Differential Cascade Voltage Switch Logic ΗΜΥ307 Δ11 Dynamic CMOS Circuits.35 Θεοχαρίδης, ΗΜΥ, 2018
DCVSL Example!Out Out B!B B!B A!A ΗΜΥ307 Δ11 Dynamic CMOS Circuits.36 Θεοχαρίδης, ΗΜΥ, 2018
How to Choose a Logic Style l Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing Style # Trans Ease Ratioed? Delay Power Comp Static 8 1 no 3 1 CPL* 12 + 2 2 no 4 3 domino 6 + 2 4 no 2 2 + clk DCVSL* 10 3 yes 1 4 * Dual Rail 4-input NAND q Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling. ΗΜΥ307 Δ11 Dynamic CMOS Circuits.37 Θεοχαρίδης, ΗΜΥ, 2018