ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin] Review: Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+
Review: The MOS Transistor Source n+ W Polysilicon Gate L Gate oxide Drain n+ Field-Oxide (SiO ) p substrate p+ stopper Bulk (Body) CMOS Inverter: A First Look C L
CMOS Inverter: Steady State Response V OL = V OH = V M = f(r n, R p ) R p = = R n = = CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
Review: Short Channel I-V Plot (NMOS) I D (A).5.5.5 X -4 V GS =.5V V GS =.V V GS =.5V V GS =.V Linear dependence.5.5.5 V DS (V) NMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T =.4V Review: Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed - V DS (V) - V GS = -.V -. V GS = -.5V V GS = -.V -.4 -.6 I D (A) -.8 V GS = -.5V - X -4 PMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T = -.4V
Transforming PMOS I-V Lines Want common coordinate set,, and I Dn I DSp = -I DSn V GSn = ; V GSp = - V DSn = ; V DSp = - I Dn Vout = =.5 = =.5 V GSp = - V GSp = -.5 Mirror around x-axis = + V GSp I Dn = -I Dp Horiz. shift over = + V DSp CMOS Inverter Load Lines PMOS = V.5 X -4 NMOS =.5V I Dn (A) =.5V =.V.5 = V.5 =.5V =.V V =.5V in = V =.5V.5.5.5 (V) =.V =.5V =.5V =.V =.5V = V.5um, W/L n =.5, W/L p = 4.5, =.5V, V Tn =.4V, V Tp = -.4V
CMOS Inverter VTC.5 (V).5.5.5.5.5 (V) CMOS Inverter VTC.5 NMOS off PMOS res NMOS sat PMOS res (V).5 NMOS sat PMOS sat.5.5.5.5 (V) NMOS res PMOS sat NMOS res PMOS off
CMOS Inverter: Switch Model of Dynamic Behavior R p C L R n C L = = CMOS Inverter: Switch Model of Dynamic Behavior R p C L R n C L = = Gate response time is determined by the time to charge C L through R p (discharge C L through R n )
Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics Switching Threshold V M where = (both PMOS and NMOS in saturation since V DS = V GS ) V M r /( + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V DSATn (V M -V Tn -V DSATn /) = (W/L) n k p V DSATp ( -V M +V Tp +V DSATp /)
Switch Threshold Example In our generic.5 micron CMOS process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V DSAT (V).63 - k (A/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p (W/L) n = Switch Threshold Example In our generic.5 micron CMOS process, using the given process parameters, a =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V).43 -.4 γ(v.5 ).4 -.4 V DSAT (V).63 - k (A/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p 5 x -6.63 (.5.43.63/) = x x = 3.5 (W/L) n -3 x -6 -. (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v
Simulated Inverter V M V M (V).5.4.3...9.8. ~3.4 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward GND Noise Margins Determining V IH and V IL 3 By definition, V IH and V IL are where d /d = - (= gain) V OH = V OL = GND VIL V M A piece-wise linear approximation of VTC VIH NM H = -V IH NM L = V IL -GND Approximating: V IH = V M -V M /g V IL = V M + ( -V M )/g So high gain in the transition region is very desirable
CMOS Inverter VTC from Simulation (V).5.5.5.5.5.5 (V).5um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = -7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance low-output =.4kΩ high-output = 3.3kΩ Gain Determinates gain - -4-6 -8 - - -4-6 -8.5.5 Gain is a strong function of the slopes of the currents in the saturation region, for = V M (+r) g ---------------------------------- (V M -V Tn -V DSATn /)(λ n - λ p ) Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing).
Impact of Process Variation on VTC Curve.5 Good PMOS Bad NMOS (V).5.5 Bad PMOS Good NMOS Nominal.5.5.5 (V) Process variations (mostly) cause a shift in the switching threshold Scaling the Supply Voltage (V).5.5 (V)..5..5.5.5.5 (V) Device threshold voltages are kept (virtually) constant.5 Gain=-.5..5. (V) Device threshold voltages are kept (virtually) constant
CMOS Inverter Layout Out metal metal In metal-poly via polysilicon pdiff metal-diff via GND PMOS (4/.4 = 6/) NMOS (/.4 = 8/) ndiff metal-metal via