Content MIS Capacitor Accumulation Depletion Inversion MOS CAPACITOR 1
MIS Capacitor Metal Oxide C ox p-si C s Components of a capacitance model for the MIS structure 2
MIS Capacitor- Accumulation ρ( x) metal x d ox insulator semiconductor ε ox d ox + + + + Charge distribution under accumulation conditions, that is, when the metal held at negative potential relative to the semiconductor. Both charges are made up of mobile carriers, electrons in the metal and holes in the semiconductor. The charges are concentrated very close to the interface surfaces. The capacitance is essentially that of a capacitor made up of the oxide as a dielectric and the metal and silicon forming the plates. There is an ample supplyof mobile carriers to connect to these two effective plates to the bulk semiconductor and bulk metal regions (the wires connecting to the plates) C C ox = Aε d ox ox 3
MIS Capacitor- Depletion ρ( x) Depletion W d x The charge distribution under depletion conditions, that is, when the metal held at a small positive potential relative to the semiconductor. There is a depletion of holes leaving negatively charged immobile acceptors ions near the surface. The width of the depletion region in the p-type depends on the applied voltage. metal + + + + d ox insulator semiconductor C ox Csd( V) ε ox The total capacitance is the series combination of the oxide capacitance and the depletion capacitance. Thus the capacitance is less than the accumulation state capacitance. Similar to the pn capacitance: C sd sen A ε 2V A d ox Total capacitance: CoxCsd C = C + C ox sd 4
Idealised MIS- Positive Bias on Metal- Inversion ev φpx -- --- -- φpf E C E i E f E V As voltage V increases an inversion layer of electrons forms at the surface of the semiconductor. The depletion region in the semiconductor increases as V increases until strong inversion occurs. Thus depletion capacitance reaches a minimum at the onset of the strong inversion point: E f tal Met V Insulator Semicond ductor φ pinv = 2 φ The mobile electrons in the semiconductor are created under equilibrium conditions that maintain a constant value for the product np. pf ρ( x) x This occurs through quite a slow process of generation/recombination. Thus the inversion layer cannot change rapidly with changing applied voltage. 5
Q M ρ( x) MIS Capacitor- Strong Inversion N A At the strong inversion point φpinv φpx = 2φpf 2kTln ni d ox W dmax Depletion width W 2ε φ N 4ε kt ln ni e N s s pinv dmax = = 2 ena A A Q n Q d x The total immobile negative charge in the maximum width depletion region : Q = ean d A W dmax The total charge on the metal is equal to the charge in the inversion layer plus the charge in the depletion region: ( ) Q = Q + Q = ean W Q m d n A d n 6
MIS Capacitor- Strong Inversion Q M ρ( x) The voltage across the MIS capacitor : φpx V= Vox + e d ox Q n W dmax Q d x The voltage across the oxide insulator: Q d ean W d Q d m A d n Vox = = εox εox εox The voltage across the MIS capacitor at the onset of strong inversion is referred to as the threshold voltage Electric Field Electron Potential V ox φ px V φpinv VTh = Voxi + = Voxi + e ean W d A dmax A = + ln εox e ni ( φ ) 2kT 2φ 2eε sna 2 pf 2kT N A = + ln Cox e ni e pf N 7
MIS Capacitor- Strong Inversion Q M ρ( x) At the onset of strong inversion: Qd >> Q n d ox W dmax x ( ) Q = Q + Q Q = ean W m inv d inv n inv d inv A dmax = A 2eε N 2 ( φ ) s A pf Thus Q n Q d The incremental capacitance can be found from: dq Q( V( t+ )) Q( V( t)) C = for V( t+ ) V( t) 0 dv V( t+ ) V( t) 8
MIS Capacitor- Frequency Dependence dq Q( V( t+ )) Q( V( t)) C = for V( t+ ) V( t) 0 dv V( t+ ) V( t) Under inversion conditions there are two components to, Q( V( t)),namely, immobile depletion region charge and mobile inversion layer electrons. {[ d d ] [ n n ]} Q( V( t+ )) Q( V( t)) = Q ( V( t+ )) Q ( V( t)) + Q ( V( t+ )) Q ( V( t)) ( Q + Q ) d n The magnitude of the change in the two components depends on how rapidly the voltage changes. 9
MIS Capacitor- Low Frequency Slow Rate Change: The voltage changes slowly enough so that the system is always close to equilibrium then there is a contribution from both components Q d, Q n Q d Q n the depletion component decreases as the voltage increases and the change virtually ceases in the strong inversion region: Q ean ( ) d A W dmax the inversion charge component increases as the voltage increases and dominates the capacitance which is determined by the location of the inversion layer charge in the semiconductor and the positive charge in the metal, namely, C ox C C ox Low Frequency 1 Accumulation Depletion Inversion V 10
MIS Capacitor- High Frequency Rapid rate of change: If the voltage changes so rapidly that the generation of the inversion layer cannot keep up then there will be little change in the inversion charge component, that is, 0. The depletion charge change, C C Q n Low Frequency Q d, dominates. The incremental capacitance of the structure is now very similar to the capacitance under the depletion regime and reaches a minimum at the maximum depletion width when inversion occurs. C ox 1 High Frequency Practical MOS structures deviate from the ideal structure : Charges within the oxide layer and at the oxide semiconductor interface. Not a flatband energy diagram due to differences in the work function of the metal and semiconductor. Accumulation Depletion Inversion V V TO Critical voltage at which a significant level of inversion occurs (the subscript o indicates substrate is at zero potential). 11
MIS Structure Frequency Independent C n+ V p metal oxide A MOS structure with an n+ connection to the capacitor. Under inversion conditions the n+ has an abundant supply of mobile majority carriers, electrons, to feed the inversion layer. Thus the capacitance characteristics of this structure follow the low frequency characteristics up to high frequencies. 12
MOS Capacitor Non Flat Band Vacuum level eχ (SiO 2 o ) 0.95eV 4.1eV eφ m 3.15eV 3.2eV eχ p 4.15eV Si 5eV eφ p 4.32eV E fm 0.9eV 8.0eV E g (SiO 2 ) E g (Si) 1.12eV 0.85eV Ec E i eφ f E f E V 0.27eV Aluminium Silicon Dioxide p-si Energylevelsfor a MOS structure. p-type material that has a doping level. The work function difference between the metal and the p-type : NA 2 10 cm 5 3 ( ) φpm = φp φm = 5 4.1 = 0.9eVolts 13
MOS Capacitor Non Flat Band E fm 3.15eV ev ox φ pb 3.2eV 1.12eV 0.85eV Ec Ei E f EV The work function of the metal is less than that of the semiconductor and electrons will flow from the metal to the semiconductor (via external circuit). The metal will have a positive surface charge. The balancing negative in the p-type results from reduction in mobile holes leaving ionised negative immobile acceptors. Aluminium Silicon Dioxide p-si V =0 Note band bending depletion of holes ionized acceptors negative space charge. Also small increase in mobile electrons. 3.2 eφ + 0.85= 3.15+ V V + eφ = 0.9 ox pb pb ox Thus, the difference in the work function between the metal and the p-type of 0.9V is distributed across the oxide, V, and the space charge region in the p-type, eφ. Not flat band ox pb 14
MOS Capacitor Non Flat Band Q M ρ( x) d ox x Electric Field Electron Potential φ pb V ox V=0.9 ev 15
MOS Capacitor Metal Negative Bias φ = φ φ pm p m 3.15eV 3.2eV Apply flatband potential ev = φ φ = 0.9 FB p m ev Efm 0.9eV 1.12eV 0.85eV Ec E i Now have flat band and there is no charge on any part of the structure. E f EV Aluminium Silicon Dioxide p-si VFB = 0.9V The characteristics of the MOS are similar to the ideal MIS except that there is a built in potential due to the difference between the work function of the metal and p-type. The offset is the flatband voltage: V FB φ φ p m = e 16
Content MOS TRANSISTORS First Order MOSFET Phenomena Cut Off Ohmic/Triode Saturated 17
MOS Transistor n + SOURCE GATE n + DRAIN W L metal source V GS gate SiO 2 drain n+ n+ p Intel L ~ 45 nm (45 X 10-9 m) Channel region(n by inversion) 18
MOS Transistor Symbols p D D D G B G G N Channel S S S D D D G B G G P Channel S S S n 19
MOS Transistor Key Dimensions p-type Silicon substrate t ox n + Oxide n + n+ ion implanted source and drain regions Metal or poly silicon gate P Substrate BULK Thin gate insulation oxide with small overlap over sourceand drain (t ox ). LD L eff Y A channel region between source and drain and undergate ( length L and width W) n + SOURCE GATE L n + DRAIN W Note that the MOSFET structure is symmetric with respect to the source and drain if all the four terminals G,S,B,D are unconnected. L W L A key parameter of a FET is the so called design geometry. Intel L ~ 45 nm (45 X 10-9 m) 20
First Order MOSFET Phenomena For simplicity we assume that in what follows VFB > 0 Flat band voltage V = GS 0 drain n+ n+ p Depletion layer ForV GS =0 a depletionlayer isformed under the drain and source. n + p junctions zero bias as studiedin the gate the MOS capacitor (non flatband model). No currents flow. 21
First Order MOSFET Phenomena V 0 GS drain n+ n+ p -------------------------- ξ +++++++++++++++++++++ ++ p Charge on metal V Depletion layer Accumulation layer Depletion layer Surface hole accumulation For V 0 GS, the region inthe p-type under the gate isan accumulationof holes. No conduction paths for currents exist due to the drain and source depletion regions that interface to the p type and the insulatorthat interfaces the p-type to the metal. The only currents that can flow under the condition are small reverse leakage currents. 22
First Order MOSFET Phenomena V GS > V drain FB Charge on metal n+ n+ p + + + + + + + + ξ p - - - - - - - - V Depletion layer Ionised acceptors For a small positive V GS bias up to a value slightly greater than V FB a depletion region also forms under the gate. The depletionregion grows as V GS increases. The only currents that can flow under the condition are small reverse leakage currents. 23
First Order MOSFET Phenomena VGS VFB drain n+ n+ p Depletion layer Inversion layer For V GS V FB the depletion region under the gate no longer grows. An inversion layer consisting of mobile electrons forms under the gate. Electronsare majority carriers in n + regions under the source and drain Thus there is an ample supply of carriers and a current can be supported by the channel of electrons under the gate if a voltage is applied between source and drain. 24
MOSFET Cut Off 0<V < V drain GS FB n+ n+ p I DS VDS > 0 VDS > 0 0<V < V GS FB Depletion layer The drain current is approximately zero since the depletion region extends from source to drain. There is no conduction channel of electrons between source and drain. Note that the drain n+p junction is reverse biased for and as V GS is increased the depletion layer under the drain grows. The MOSFETissaid to be in the cut-off region. 25
MOSFET Ohmic/Triode VGS VFB drain I DS VDS > 0 n+ n+ p 0<VDS < VGS VFB V FB<VGS Depletion layer Inversion layer A strong inversion layer is produced near the source. Since there is a potential rise from the source to drain the potential of the gate to the p- type degree of inversion decreases along the region from source to drain ( V GP =V GS -V SP, 0<V SP <V DS ). Provided that V DS is not too large then a strong inversion channel will exist from source to drain and this channel will behave like a resistor, that is the voltage rise along the channel is linearly related to the current through the channel. The resistance of the channel is a function of the gate to source voltage since it controls the density of the carriers in the inversion layer. This region of operation of the MOSFET is called the triode region or ohmic region. 26
MOSFET Ohmic/Triode VGS VFB drain I DS VDS > 0 n+ n+ p 0<VDS < VGS VFB V FB<VGS Depletion layer Inversion layer Recall that for the MIS capacitor, the increase in capacitance in inversion only occurs if the generation/recombination of electrons can keep up with the applied ac signal. In practice, R/G rates are relatively slow so that the capacitance does not increase above a frequency of about 100Hz for the Si-SiO2 system. In the presence of some additional reservoir of electrons, the low frequency behaviour may be extended well into the MHz range. This is the case for a MOSFET where the reservoir is the source and drain n+ regions. Note that the current in the channel is a current between source and drain and not from the p substrate! 27
MOSFET Saturated VGS VFB drain n+ n+ p I DS V >V V DS GS FB VDS > 0 V >V V DS GS FB Depletion layer Inversion layer ForagivenV GS the drain current increasesas V DS increasesfrom zero. GS Butnear the channel V GP decreases. As V DS is increased a point is reached where V GP is so small that only a small amount of inversions occurs and this effectively starts to increase the resistance locally and prevents further increase in current. An equilibrium conditions is reached an the channel in the p-type is pinched off at the drainend where its thicknessis reduced to a very smallvalue. At pinch off the current reaches a limiting value and hence the device is set to be in a saturated mode (the current is saturated). DS 28
MOSFET Saturated Source Channel Drain V G V G-channel V DS V T Pinch-off 29
MOSFET Static Characteristics Pinch Off I DS V GSN More posi itive 0 1 2 3 4 5 V DS 30
Static MOSFET Model The gate to source voltage that produces the onset of strong inversion for zero drain to source voltage will be called the threshold voltage and denoted by V Th,V TN, and V TP dependingon the context. V Th V TN V TP thegenericsymbol fornchannel forpchannel 2eε N V = V + 2 + V + 2φ ( ( )) φ pf s A Th FB B Cox TX ( ( ) ) pf B pf =V + γ 2φ + V 2φ pf γ body factor and typicallyis inthe range 0.1 1 31
MOSFET n channel Enhancement Devices V V > GSN < VTN VDSN 0 IDN = 0 TN 0 I DSN V GSN More positive Cut Off: Ohmic/Triode Region: VGSN > VTN VGDN > VTN V > V V > V GSN TN GDN TN 1 I = k V V V V 2 ( ) 2 DN N GSN TN DSN DSN V = V + V = V + V = V V DSN DGN GSN GDN GSN GSN GDN VDSN < VGSN VTN V GDN > V TN V DSN 0 1 2 3 4 5 k k N ' N WN µ eεox ' W N = = kn LN tox LN = µ C e oxn Saturation: V > V V < V GSN TN GDN TN 0 V V V GSN TN DSN V V V 0 DSN GSN TN kn IDN = ( VGSN VTN) 2 2 32
Channel Length Modulation I DSN V GSN More positive 1 λ 0 1 2 3 4 5 V DSN Channellength variation due to the applied V DSN I k V V V 2 ( ) N 2 DN = ( GSN TN) 1+λN DSN λ N empirically determined parameter 33
MOSFET p channel Enhancement Devices V TP < 0 -I DSP Cut Off: V V > 0 V < 0 I = 0 GSP TP DSP DP V GSP More negative -V DSP Ohmic/Triode Region: 0> VDSP > ( VGSP VTP) 1 I = k V V V V 2 ( ) 2 DP P GSP TP DSP DSP Saturation: 0 V V V V < 0 GSP TP DSP DSP kp IDP = ( VGSP VTP) 2 2 k k P ' p WP µ hεox ' W P = = kp LP tox LP = µ C h oxp Allowing for channel length modulation I k V V V 2 ( ) P 2 DP = ( GSP TP) 1 λp DSP 34
Identifying Region of Operation n channel V GSN < V TN YES Cutoff NO V > V GDN TN Large enough gate to substrate voltage to cause inversion VDSN < VGSN VTN YES Triode NO Saturated 35
Identifying Region of Operation p channel V GSP > V TP YES Cutoff NO V < V GDP TP Large enough gate to substrate voltage to cause inversion V < 0 & V < V V > V TP GDP TP GDP TP eg.. V = 4V V = 6V V < V TP GDP GDP TP but V = 6V > V = 4V GDP TP VDSP > VGSP VTP YES Triode NO Saturated 36
MOSFET Depletion Devices In a depletion mode device a channel between source and drain exists for a zero gate to source voltage. To remove the channel (at the source end) and turn the transistor off requires the application of an appropriate gate to source voltage. For an n channel a negative voltage is required to turn off the transistor. V TND <0 for an n channeldepletiondevice. D ma I D 0 TN V < V E > 0 TN 2 1.5 D 1 G B 0 V GS -2-1 0 1 2 DEPLETION MODE ENHANCEMENT MODE S 37
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