VLSI Design The MOS Transistor

VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1

Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance Body effect Process corners CMOS VLSI Design 4th Ed. 2

Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C ( V/ t) -> t = (C/I) V Capacitance and current determine speed CMOS VLSI Design 4th Ed. 3

MOS Capacitor Gate and body form MOS capacitor polysilicon gate silicon dioxide insulator p-type body Operating modes Accumulation Depletion Inversion 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 4

MOS Cap - Accumulation V g < 0 + - polysilicon gate silicon dioxide insulator p-type body (a) 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 5

MOS Cap - Depletion 0 < V g < V t depletion region + - (b) v t - Threshold voltage: characteristic parameter of a transistor 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 6

MOS Cap - Inversion V g > V t + - inversion region depletion region (c) 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed. 7

Terminal Voltages Mode of operation depends on V g, V d, V s V g V gs = V g V s V gd = V g V d V gs V gd V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V s V ds V d CMOS VLSI Design 4th Ed. 8

nmos Cutoff No channel I ds 0 V gs = 0 + - g + - V gd s d n+ n+ p-type body b CMOS VLSI Design 4th Ed. 9

nmos Linear Channel forms V gs > V t + - g + - V gd = V gs s n+ n+ d V ds = 0 p-type body b CMOS VLSI Design 4th Ed. 10

nmos Linear If 0 < V ds < V gs - v t Current flows from drain to source (e - from s to d) I ds increases with V ds Similar to linear resistor V gs > V t + - g + - V gs > V gd > V t s d I ds n+ n+ 0 < V ds < V gs -V t p-type body b CMOS VLSI Design 4th Ed. 11

nmos Saturation Channel pinches off (e - still flow due to drift) I ds independent of V ds We say current saturates Similar to current source V gs > V t + - g + - V gd < V t s d I ds n+ n+ V ds > V gs -V t p-type body b CMOS VLSI Design 4th Ed. 12

nmos Saturation cont d Drift depends on electric field E drift between drain and pinch-off E drift V ds /L drift pinch-off) (L drift = Distance between drain and If V ds increases L drift increases E drift stays constant Equilibrium between V ds, L drift and E drift pinch-off L drift n+ n+ p-type body CMOS VLSI Design 4th Ed. 13

nmos I-V Curve Drain Current I ds (log scale) Linear Region V gs - v t Saturation Region Gate to Source Voltage V gs Drain to Source Voltage V ds MOS Transistor Theory CMOS VLSI Design 4th Ed. 14

Quiz In which transistor operating region a channel is formed? A. Cut-off B. Linear C. Saturation D. Accumulation Under which condition a channel is formed? A. V gs < V th, 0 < V ds B. V gs > V th, 0 = V ds C. V gs > V th, V ds > V gs D. V gs < V th, 0 < V ds MOS Transistor Theory CMOS VLSI Design 4th Ed. 15

I-V Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? CMOS VLSI Design 4th Ed. 17

Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion (Gate oxide channel) Q channel = CV C = C g = k ox *ε 0 WL/t ox = C ox WL t ox polysilicon gate W C ox = k ox *ε 0 = ε ox / t ox n+ n+ L p-type body CMOS VLSI Design 4th Ed. 18

Channel Charge cont d V = V gc v t (voltage attracting charge to channel beyond min. required to invert p to n) V c = (V s + V d )/2 (average voltage between V s and V d ) = V s + V ds /2 V gc = V g V c = V gs V ds /2 V = (V gs + V gd )/2 - v t = (V gs V ds /2) - v t Q channel = C ox WL * [(V gs - V ds /2) - v t ] CMOS VLSI Design + + source V gs C g V gd drain - - channel n+ - + n+ V s 4th Ed. gate V g V ds p-type body V d

Channel Charge cont d Why V = V gc v t? v t is required for inverting the channel related charge Q = C g * v t not available for current, i.e. not inside channel gate + + source V gs C g V gd drain - - channel n+ - + n+ V s V g V ds p-type body V d MOS Transistor Theory CMOS VLSI Design 4th Ed. 20

Carrier velocity Charge is carried by e - (nmos) Electrons are propelled by the lateral electric field between source and drain E = V ds /L Carrier velocity v proportional to lateral E-field v = µe µ called mobility Time for carrier to cross channel: t = L / v CMOS VLSI Design 4th Ed. 21

nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Qchannel = t W V = µ C V v V L V = β V ds gs v t V 2 ds ds ox gs t 2 ds W β = µcox L CMOS VLSI Design 4th Ed. 22

nmos Saturation I-V If V gd < v t, channel pinches off near drain When V ds > v dsat with v dsat = V gs v t Now drain voltage no longer increases current v I = β V v dsat v 2 β = ( V ) 2 gs vt 2 ds gs t dsat CMOS VLSI Design 4th Ed. 23

nmos I-V Summary Shockley 1 st order transistor models (long channels > 2 µm) 0 Vgs < v V I = β V v ds V V v 2 < β ( V v ) 2 V > v 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation CMOS VLSI Design 4th Ed. 24

Example AMI Semiconductor 0.6 µm process t ox = 100 Å µ = 350 cm 2 /V*s v t = 0.7 V ε ox = 3.9 * 8.85 * 10-14 F/cm Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ 350 120 μa/v 100 10 14 W 3.9 8.85 10 W W β = µcox = ( ) L 8 = L L CMOS VLSI Design 4th Ed. 25 2

Example AMI Semiconductor 0.6 µm process 2.5 V gs = 5 2 I ds (ma) 1.5 1 V gs = 4 V gs = 3 0.5 V gs = 2 V gs = 1 0 0 1 2 3 4 5 V ds CMOS VLSI Design 4th Ed. 26

pmos I-V All dopings and voltages are inverted for pmos Source is the more positive terminal Mobility µ p is determined by holes Typically 2-3x lower than that of electrons µ n 120 cm 2 /V s in AMI 0.6 µm process Thus pmos must be wider to provide same current In this class, assume µ n / µ p = 2 CMOS VLSI Design 4th Ed. 27

pmos I-V 0-0.2 V gs = -3 V gs = -2 V gs = -1 I ds (ma) -0.4 V gs = -4-0.6 V gs = -5-0.8-5 -4-3 -2-1 0 V ds CMOS VLSI Design 4th Ed. 28

Quiz Given a following parameters: tox = 5 nm, v t = 0.5 V, µ = 350 cm²/v*s, ε ox = 3.9 * 8.85 * 10-14 F/cm, V gs = V ds = 3.3 V, W = 1 µm, L = 0.5 µm What is the Channel charge? β What is? MOS Transistor Theory CMOS VLSI Design 4th Ed. 29

Quiz Given a following parameters: tox = 5 nm, v t = 0.5 V, µ = 350 cm²/v*s, ε ox = 3.9 * 8.85 * 10-14 F/cm, V gs = V ds = 3.3 V, W = 1 µm, L = 0.5 µm What is the Channel charge? Q channel = CV = ε ox / t ox * WL * [(V gs - V ds /2) - v t ] Q channel = 69 nf/cm² *WL * [(V gs - V ds /2) - v t ] = 0.3 fc β What is? β = µ C ox = 350 69 48.3µ L Vs = cm L V 2 W cm nf W A 2 2 MOS Transistor Theory CMOS VLSI Design 4th Ed. 30

Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion CMOS VLSI Design 4th Ed. 31

Capacitance Gate C gso C gs C gd C gb C gdo Source - Drain C sb C db Body MOS Transistor Theory CMOS VLSI Design 4th Ed. 32

Gate Capacitance For simplification: approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W polysilicon gate W t ox L n+ n+ p-type body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) CMOS VLSI Design 4th Ed. 33

Gate Capacitance detailed Parameter Cutoff Linear Saturation C gb C 0 0 0 C gs 0 C 0 /2 2/3 C 0 C gd 0 C 0 /2 0 C g = C gs + C gd + C gb C 0 C 0 2/3 C 0 V gs > v t v t V gs - v t V ds MOS Transistor Theory CMOS VLSI Design 4th Ed. 34

Gate Capacitance cont d Cut-off No channel => changes on V g don t affect charge on drain/source Linear Channel acts as bottom plate (no capacitance between gate and bulk) Charge (roughly) shared between drain and source Saturation Charge only at source region MOS Transistor Theory CMOS VLSI Design 4th Ed. 35

Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Arise from p-n junctions between drain/source and body depletion region (no free carriers) acts as insulator Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diffusion ½ C g for uncontacted diffusion (smaller area) Varies with process CMOS VLSI Design 4th Ed. 36

Diffusion Capacitance CMOS VLSI Design 4th Ed. 37

Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 38

Outline Nonideal Transistor Behavior High Field Effects Mobility Degradation Velocity Saturation Channel Length Modulation Threshold Voltage Effects Body Effect Drain-Induced Barrier Lowering Short Channel Effect Process and Environmental Variations CMOS VLSI Design 4th Ed. 39

Ideal Transistor I-V Shockley long-channel transistor models 0 Vgs < V V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation CMOS VLSI Design 4th Ed. 40

Ideal vs. Simulated nmos I-V Plot I ds (µa) 1200 1000 800 600 Ideal 65 nm IBM process, V DD = 1.0 V V gs = 1.0 V gs = 0.8 400 V gs = 0.6 200 V gs = 0.4 0 0 0.2 0.4 0.6 0.8 1 V ds (V) CMOS VLSI Design 4th Ed. 41

Ideal vs. Simulated nmos I-V Plot 1200 I ds (µa) Simulated Ideal 65 nm IBM process, V DD = 1.0 V 1000 800 600 V gs = 1.0 400 200 0 0 0.2 0.4 0.6 0.8 1 V gs = 0.8 V gs = 0.6 CMOS VLSI Design 4th Ed. 42

Ideal vs. Simulated nmos I-V Plot I ds (µa) 1200 1000 800 600 Simulated Ideal 65 nm IBM process, V DD = 1.0 V Velocity saturation & Mobility degradation: Saturation current increases less than quadratically with V gs V gs = 1.0 400 200 0 0 0.2 0.4 0.6 0.8 1 V gs = 0.8 V gs = 0.6 CMOS VLSI Design 4th Ed. 43

Ideal vs. Simulated nmos I-V Plot 1200 1000 I ds (µa) Simulated Ideal 65 nm IBM process, V DD = 1.0 V Channel length modulation: Saturation current increases with V ds 800 600 400 V gs = 1.0 V gs = 0.8 200 0 0 0.2 0.4 0.6 0.8 1 V gs = 0.6 CMOS VLSI Design 4th Ed. 44

Ideal vs. Simulated nmos I-V Plot I ds (µa) 1200 1000 800 600 Simulated Ideal 65 nm IBM process, V DD = 1.0 V Velocity saturation & Mobility degradation: I on lower than ideal model predicts I on = 747 ma @ V gs = V ds = V DD V gs = 1.0 400 200 0 0 0.2 0.4 0.6 0.8 1 V gs = 0.8 V gs = 0.6 CMOS VLSI Design 4th Ed. 45

ON and OFF Current I on = I ds @ V gs = V ds = V DD Saturation 1000 800 I ds (µa) I on = 747 ma @ I on = 747 ma @ V gs = V gs ds = V ds = V DD DD V gs = 1.0 600 V gs = 0.8 400 200 V gs = 0.6 V gs = 0.4 0 0 0.2 0.4 0.6 0.8 1 V ds CMOS VLSI Design 4th Ed. 46

ON and OFF Current I off = I ds @ V gs = 0, V ds = V DD Cutoff CMOS VLSI Design 4th Ed. 47

Electric Fields Effects Vertical electric field: E vert = V gs / t ox Attracts carriers into channel Long channel: Q channel E vert Lateral electric field: E lat = V ds / L Accelerates carriers from drain to source Long channel: v = µe lat CMOS VLSI Design 4th Ed. 48

Coffee Cart Analogy Tired student runs from VLSI lab to coffee cart Freshmen are pouring out of the physics lecture hall V ds is how long you have been up Your velocity = fatigue mobility V gs is a wind blowing you against the glass (SiO 2 ) wall At high V gs, you are buffeted against the wall Mobility degradation At high V ds, you scatter off freshmen, fall down, get up Velocity saturation Don t confuse this with the saturation region CMOS VLSI Design 4th Ed. 49

Mobility Degradation High E vert effectively reduces mobility Collisions with oxide interface Universal model form [Chen96] CMOS VLSI Design 4th Ed. 50

Mobility Degradation - Example Effective mobility of NMOS, PMOS when fully on? (65 nm, VDD = 1V, v t = 0.3 V, µ estimated-n = 80 cm 2 /V, t ox = 10.5 Å) V gs = 1 V t ox = 1.05 nm µ eff-n = 96 cm 2 /V; µ eff-p = 36 cm 2 /V CMOS VLSI Design 4th Ed. 51

Velocity Saturation At high E lat, carrier velocity rolls off Carriers scatter off atoms in silicon lattice Velocity reaches v sat Electrons: 10 7 cm/s Holes: 8 x 10 6 cm/s CMOS VLSI Design 4th Ed. 52

Velocity Saturation Better model E c : critical electric field v sat : saturated carrier velocity Critical voltage V c : V ds at which E c is reached V c = E c L CMOS VLSI Design 4th Ed. 53

Velocity Saturation - Example What is V c for fully on NMOS, PMOS? (using values from mobility example) V c = Ec L E c = v µ 2 sat eff 1 v sat = NMOS :10 ; PMOS : 8 10 7 cm 6 s cm s ( 7 ) ( ) ( 2 cm 6 cm ) V = 2 10 6.5 10 cm 96 = 1.35 V c n s Vs 1 ( 6 ) ( ) ( 2 cm 6 cm ) V = 2 8 10 6.5 10 cm 36 = 2.89 V c p s Vs 1 CMOS VLSI Design 4th Ed. 54

Vel Sat, Mob I-V Effects New Model considering modility degardation and velocity saturation 0 Vgs v < µ ( ) eff Vgs W V I = C V v ds V V V V 2 < ds 1+ L Vc CWV ( v V ) v V > V ds ox gs t ds ds dsat ox gs t dsat sat ds dsat t CMOS VLSI Design 4th Ed. 55

Vel Sat I-V Effects Ideal transistor ON current increases with V DD 2 ( Vgs vt ) W β I = µ C = V v L 2 2 2 ( ) ds ox gs t Velocity-saturated ON current increases with V DD ( ) I Cox W V v v for V > V ds gs t sat ds c Real transistors are partially velocity saturated Approximate with α-power law model I ds V α DD 1 < α < 2 determined empirically ( 1.3 for 65 nm) 2 CMOS VLSI Design 4th Ed. 56

α-power Model 0 Vgs < Vt cutoff Vds Ids = Idsat Vds < Vdsat linear Vdsat Idsat Vds > Vdsat saturation β I = P V V 2 ( ) dsat c gs t α ( ) /2 V = P V V dsat v gs t α α, β, P c, P v empirically estimated parameters Poor fit for low V ds Good fit for V ds = V DD for complete range of V gs CMOS VLSI Design 4th Ed. 57

α-power Model CMOS VLSI Design 4th Ed. 58

Channel Length Modulation Reverse-biased p-n junctions form a depletion region Region between n and p with no carriers Width of depletion L d region grows with reverse bias L eff = L L d GND Source V DD Gate V DD Drain Depletion Region Width: L d n + L L eff p GND n + bulk Si CMOS VLSI Design 4th Ed. 59

Channel Length Modulation Reminder: what happens in depletion region between pinch-offed channel and drain? Electron concentration in depletion small (but not zero) Electrons move fast because electric field is very high There is no barrier to electron flow (on the contrary!) Shorter L eff gives more current I ds increases with V ds Even in saturation CMOS VLSI Design 4th Ed. 60

Channel Length Modulation µcox W I = V v 2 L L ( ) dsat gs t d β ( ) 2 = V v ( 1 + λvd s ) with λ = 2 2 L L d 1 gs t ds V λ = channel length modulation coefficient no feature size Empirically fit to I-V characteristics Less important for digital designer Very important for analog designer (reduction of amplifier gain) CMOS VLSI Design 4th Ed. 61

Threshold Voltage Effects v t is V gs for which the channel starts to invert Ideal models assumed v t is constant Really depends (weakly) on almost everything else: Body voltage: Body Effect Drain voltage: Drain-Induced Barrier Lowering Channel length: Short Channel Effect CMOS VLSI Design 4th Ed. 62

Body Effect Body is a fourth transistor terminal V sb affects the charge required to invert the channel Increasing V s or decreasing V b increases v t (carriers in channel are attracted to bulk terminal and removed from channel => higher Vgs required) ( ) N A vt = vt0 + γ φs + Vsb φs φ s = 2vT ln ni φ s = surface potential at threshold Depends on doping level N A and intrinsic carrier concentration n i γ = body effect coefficient t = 2qε N = 2qε N ox si A si A ε ox Cox CMOS VLSI Design 4th Ed. 63

Drain Induced Barrier Lowering (DIBL) V gs < V th V gs > V th Source Gate V ds Drain Source Gate V ds Drain Potential Height of curve = Potential barrier Changed by gate voltage Electrons have to overcome potential barrier to enter the channel Ideal: Potential barrier is only controlled by gate voltage 64

Drain Induced Barrier Lowering cont d Long-channel transistor (L > 2 µm) Short-channel transistor (L < 180 nm) Gate V ds G V ds Source Drain S D Lowering of potential barrier V ds = V th V ds = V th V ds = V DD V ds = V DD At short channel transistors potential barrier is also affected by drain voltage If V ds = V DD Transistors can start to conduct even if V gs < v th 65

DIBL Drain-Induced Barrier Lowering Drain voltage also affect V t v t = vt ηvds η DIBL coefficient High drain voltage causes current to increase. ttdsvvvη CMOS VLSI Design 4th Ed. 66

Short Channel Effect In small transistors, source/drain depletion regions extend into the channel Impacts the amount of charge required to invert the channel And thus makes v t a function of channel length Short channel effect: v t increases with L CMOS VLSI Design 4th Ed. 67

Quiz Which of the following effects increases mobility degradation? A. Thinner gate oxide B. Thicker gate oxide C. Higher V gs D. Lower V gs Which of the following effects reduces the threshold voltage A. Higher body voltage V b B. Lower body voltage V b C. Lower V ds in sub-100nm technologies D. Higher V ds in technologies with L > 2 µm MOS Transistor Theory CMOS VLSI Design 4th Ed. 68

Quiz Which of the following effects increase(s) mobility degradation? A. Thinner gate oxide B. Thicker gate oxide C. Higher V gs D. Lower V gs Which of the following effects reduces the threshold voltage A. Higher body voltage V b B. Lower body voltage V b C. Lower V ds in sub-100nm technologies D. Higher V ds in technologies with L > 2 µm MOS Transistor Theory CMOS VLSI Design 4th Ed. 69

Temperature Sensitivity Increasing temperature Reduces mobility Reduces v t I ON decreases I OFF increases with temperature with temperature CMOS VLSI Design 4th Ed. 70

Temperature Sensitivity Lower mobility I ds Lower v t increasing temperature V gs CMOS VLSI Design 4th Ed. 71

So What? So what if transistors are not ideal? They still behave like switches. But these effects matter for Supply voltage choice Logical effort Quiescent power consumption Pass transistors Temperature of operation CMOS VLSI Design 4th Ed. 72

Parameter Variation Transistors have uncertainty in parameters Process: L eff, V t, t ox of nmos and pmos Vary around typical (T) values Fast (F) L eff : short V t : low t ox : thin Slow (S): opposite Not all parameters are independent for nmos and pmos slow fast pmos slow SF SS TT nmos FF FS fast CMOS VLSI Design 4th Ed. 73

Environmental Variation V DD and T also vary in time and space Fast: V DD : high T: low Corner Voltage Temperature F 1.98 0 C T 1.8 70 C S 1.62 125 C CMOS VLSI Design 4th Ed. 74

Process Corners Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. Describe corner with four letters (T, F, S) nmos speed pmos speed Voltage Temperature CMOS VLSI Design 4th Ed. 75

Extra MOS Transistor Theory CMOS VLSI Design 4th Ed. 76

Gate Capacitance detailed C = ε WL / t g ox ox MOS Transistor Theory CMOS VLSI Design 4th Ed. 77

Data-dependent Gate Cap MOS Transistor Theory CMOS VLSI Design 4th Ed. 78

DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering Drain voltage also affect V t V t = Vt ηvds ttdsvvvη High drain voltage causes current to increase. CMOS VLSI Design 4th Ed. 79

Leakage What about current in cutoff? Simulated results What differs? Current doesn t go to 0 in cutoff 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 80

Leakage Sources Subthreshold conduction Transistors can t abruptly turn ON or OFF Dominant source in contemporary transistors Gate leakage Tunneling through ultrathin gate dielectric Junction leakage Reverse-biased PN junction diode current 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 81

Subthreshold Leakage Subthreshold leakage exponential with V gs Vgs Vt 0 + ηvds kv γ sb Vds e 1 e nvt vt Ids = Ids0 n is process dependent typically 1.3-1.7 Rewrite relative to I off on log scale S 100 mv/decade @ room temperature 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 82

Gate Leakage Carriers tunnel thorough very thin gate oxides Exponentially sensitive to t ox and V DD A and B are tech constants Greater for electrons So nmos gates leak more Negligible for older processes (t ox > 20 Å) From [Song01] Critically important at 65 nm and below (t ox 10.5 Å) 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 83

Junction Leakage Reverse-biased p-n junctions have some leakage Ordinary diode leakage Band-to-band tunneling (BTBT) Gate-induced drain leakage (GIDL) p+ n+ n+ p+ p+ n+ p substrate n well 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 84

Diode Leakage Reverse-biased p-n junctions have some leakage VD T I e v D = I S 1 At any significant negative diode voltage, I D = -I s I s depends on doping levels And area and perimeter of diffusion regions Typically < 1 fa/µm 2 (negligible) 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 85

Band-to-Band Tunneling Tunneling across heavily doped p-n junctions Especially sidewall between drain & channel when halo doping is used to increase V t Increases junction leakage to significant levels X j : sidewall junction depth E g : bandgap voltage A, B: tech constants 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 86

Gate-Induced Drain Leakage Occurs at overlap between gate and drain Most pronounced when drain is at V DD, gate is at a negative voltage Thwarts efforts to reduce subthreshold leakage using a negative gate voltage 4: Nonideal Transistor Theory CMOS VLSI Design 4th Ed. 87