EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1
pn Junction p-type semiconductor in contact with n-type Basic building blocks of semiconductor devices Diodes, Bipolar junction transistors (BJT), Metal-oxide-semiconductor field effect transistors (MOSFET) 2
Built-in Voltage Example: A pn junction with n-doping of 10 17 cm 3 and p-doping of 10 18 cm 3 " V 0 = V T ln N N % A D 2 ' = 0.88 V # n i & At pn junction, free electrons from n-side "recombine" with free holes from p-side. "Depletion region" has no electrons or holes, but has fixed (immobile) charges from donor and acceptor ions The fixed charges establish an electric field, and create a potential difference between p- and n-sides. This potential is called "built-in potential"! V 0 = V T ln N D # 2 & " n i % V T : thermal voltage (= 26 mv at room temp) : acceptor concentration on p-side N D : donor concentration on n-side n i : intrinsic carrier concentration (=1.5 10 10 cm 3 at room temp) 3
Simplified Analysis of pn Junction Gauss Law: E # da = ' ( ) Electrical potential: V = 1 23 E x / dx Electric Field E max 4
Detailed Electrostatic Analysis of pn Junction (1) Electric Field Emax " Charge density: q(x) = # % Gauss Law: In one dimension: 5 E!" da!!" # = Q ε S, qa, x p < x < 0 qan D, 0 < x < x n ε S =11.7ε 0 ε 0 = 8.854 10 14 F/cm E(x)A E( x p )A = qa(x + x p ) ε S E( x p ) = 0 (in charge neutral region, = p) " E(x) = # % Note: q (x + x p ) ε S, x p < x < 0 qn D (x x n ) ε S, 0 < x < x n x p = N D x n (charge equality) Maximum electrical field occurs at x = 0 (junction) E max = q x p ε S = qn Dx n ε S
Detailed Electrostatic Analysis of pn Junction (2) Electric Field " E(x) = # % V(x) = " V(x) = # % x x p q (x + x p ) ε S, x p < x < 0 qn D (x x n ) ε S, 0 < x < x n E(x')dx' q V(x n ) = q q x 2 2 ( p + N D x n ) qn D x 2 2 ( p + N D x n ) = V 0 ( x + x p ) 2, x p < x < 0 ( x x n ) 2, 0 < x < x n E max x p = N D + N D W, x n = + N D W W = 2e S q ' 1 + 1 * ),V 0 : Depletion Width ( N D + 6
Depletion Width Under Bias W = 2e S q! # " 1 + 1 N D & V 0 V % ( ) V is the applied voltage to the pn junction, it's positive for forward bias and negative for reverse bias. Depletion width is widened in reverse bias 7
Current-Voltage (I-V) Characteristics Under forward bias, minority carriers at the edge of depletion region is boosted up by (e V /V T 1) : p n (x) = p n0 + p n0 e V /V T ( 1 ) e x x n L p L p : hole diffusion length in n-type Hole diffusion current density on n-side dp J p = qd n (x) p = q D p p n0 e V /V ( T 1) dx x=x n L p Similarly, electron diffusion current density in p-side dn J n = qd p (x) n = q D n n p0 e V /V ( T 1) dx x= x p L n Total current : ( ) A = A q D p I = J p + J n I = I S e V /V T 1 " # L p p n0 + q D % n n p0 L ' ev /V T ( 1 ) n & 2 D ( ) where I S = Aqn p i " + D % n # L p N D L n N ' A & 8
I-V Curve I = I S e V /V T ( 1 ) where " 2 D I S = Aqn p i + # L p N D D % n L n N ' A & 9
Capacitance in pn Junction (1): Depletion Capacitance (Mainly Reverse Bias) Parallel plate capacitance: C j = ε sa W Plate separation, W, is voltage dependent: W = 2ε s q 1 + 1 N D V 0 + V R Variable capacitance: C j V = C j0 1 + V R V 0 10
Capacitance in pn Junction (2): Diffusion Capacitance (Forward Bias) Extra minority carriers stored outside junction under forward bias Q p = Aq shaded area under p n (x) Q p = Aq p n0 e V /V T ( 1 ) e x x n L p dx x n ( ) = L 2 p Q p = AqL p p n0 e V /V T 1 D p I p = τ p I p L p 2 D p has unit of time, its physical meaning is minority carrier lifetime: τ p = L 2 p D p 11 Similarly, Q n = τ n I n Total charge stored : Q = τ p I p +τ n I n = τ T I τ T is mean transit time These stored charges correspond to another nonlinear capacitor call "diffusion capacitance": ( ) C d = dq dv = d τ T I dv = τ T di dv C ' d = τ * T ),I ( + V T
Summary of pn Junction! Built-in potential : V 0 = V T ln# N D 2 " n i Under forward bias : ( ) I-V curve : I = I S e V /V T 1! Diffusion capacitance : C d = τ T # &I " % Under revserse bias : V T & % Negligible current, I = I S Depletion capacitance : C j = Other important parameter : Depletion Width: W = 2e S q! # " C j0 1+ V R V 0 1 + 1 N D & V 0 V % ( ) 12
Basic Semiconductor Fabrication 13
Economy of Scale 300mm and 450mm Si Wafers Current: 300mm wafers Next gen: 450mm wafers 200mm wafers are still workhorse, particularly for IoT http://wccftech.com/foundries-tsmc-companies-shift- 300mm-wafers/ Economy of scale Full CMOS has 60+ photomasks, and yet chip cost almost nothing 1K for 200mm /mm 2 10K for 300mm /mm 2 14
Basic Semiconductor Fabrication Process Learn more in EE 143 15
State of the Art Lithography Machine (EUV: Extreme Ultra Violet) 16
State of the Art Lithography Machine (EUV: Extreme Ultra Violet) 17
Microfabrication (cont d) 18
Microfabrication (cont d) 19
Microfabrication (cont d) 20
Modern CMOS IC Cross Section Intel 14nm Broadwell chip, side-on, showing all 13 layers 21
Appendix Rigorous derivation of pn junction potential Rigorous derivation of junction capacitance 22
" E(x) = # % V(x) = x x p Rigorous Derivation of pn Junction Potential q (x + x p ) ε S, x p < x < 0 qn D (x x n ) ε S, 0 < x < x n E(x')dx' (1) for x p < x < 0 :V(x) = E(x')dx' = x x p x x p q (x'+ x p ) dx' 23 ε S = q x'=x ( x'+ x p ) 2 x'= x p = q ( x + x p ) 2 (2) for 0 < x < x n : Because E(x) has different expression for x < 0 and x > 0, the integration should be performed in two separate ranges, first from x p to 0, and then from 0 to x. We can use V(x = 0) from the above equation for the first intgration. Therefore, V(x) = q = q x p x 2 qn D(x' x n ) dx' x p 0 ε S ' 2 qn D(x x n ) 2 ) ( Built-in potential : qn 2 Dx n = q *, = q + V 0 = V(x n ) = q x 2 p qn D(x' x n ) 2 x 0 x 2 p + qn 2 Dx n qn D(x x n ) 2 x 2 2 ( p + N D x n )
Rigorous Derivation of Junction Capacitance In comparision, for a "linear" (normal) capacitor: Total charge Ain depletion width at V = -V R N Q J = AqN D x n = Aq D W + N D W = 2e S q! # " 1 + 1 N D & V 0 +V R % ( ) As bias voltage change, the amount of charge in the junction change. This is a "nonlinear" capacitor. The capacitance value is C j = dq J dv R = Aq N D + N D C j = A ε S q 2! N D # & " + N D % At zero bias, V R = 0 C j0 = A ε Sq 2! N D # & " + N D % 2e S q! # " 1 ( V 0 +V R ) 1 V 0 1 + 1 N D & d % dv Note: ( V 0 +V R ) C j = ε S A W C = Q V is a constant Therefore at V = -V R, C j = 24 C j0 1+ V R V 0 This is a variable capacitor, controllable by voltage!