74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

Similar documents
74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

The 74LV32 provides a quad 2-input OR function.

The 74LV08 provides a quad 2-input AND function.

74HC238; 74HCT to-8 line decoder/demultiplexer

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

2-input EXCLUSIVE-OR gate

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74AHC1G00; 74AHCT1G00

74HC154; 74HCT to-16 line decoder/demultiplexer

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

The 74LVC1G02 provides the single 2-input NOR function.

74LV General description. 2. Features. 8-bit addressable latch

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

Dual 2-to-4 line decoder/demultiplexer

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

The 74LVC1G11 provides a single 3-input AND gate.

Octal bus transceiver; 3-state

74AHC2G126; 74AHCT2G126

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter

74HC08-Q100; 74HCT08-Q100

74AHC1G14; 74AHCT1G14

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs

The 74HC21 provide the 4-input AND function.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC244; 74HCT244. Octal buffer/line driver; 3-state

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74LVU General description. 2. Features. 3. Applications. Hex inverter

Temperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

74HC32-Q100; 74HCT32-Q100

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

74HC03-Q100; 74HCT03-Q100

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74AHC30-Q100; 74AHCT30-Q100

Dual JK flip-flop with reset; negative-edge trigger

74HC30-Q100; 74HCT30-Q100

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC594; 74HCT bit shift register with output register

74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74AHC14-Q100; 74AHCT14-Q100

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state

INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

Dual 3-channel analog multiplexer/demultiplexer with supplementary switches

74HC151-Q100; 74HCT151-Q100

8-bit binary counter with output register; 3-state

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer

74HC238; 74HCT to-8 line decoder/demultiplexer

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

The 74LVC10A provides three 3-input NAND functions.

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

Octal D-type transparent latch; 3-state

Hex inverting Schmitt trigger with 5 V tolerant input

74HC259; 74HCT259. The 74HC259; 74HCT259 has four modes of operation:

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

3-to-8 line decoder, demultiplexer with address latches

5-stage Johnson decade counter

Hex inverter with open-drain outputs

The 74LV08 provides a quad 2-input AND function.

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting

74HC2G08-Q100; 74HCT2G08-Q100

74HC153-Q100; 74HCT153-Q100

74HC1G125; 74HCT1G125

74HC280; 74HCT bit odd/even parity generator/checker

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G02-Q100; 74HCT1G02-Q100

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

BCD to 7-segment latch/decoder/driver

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state

74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate

74AHC541-Q100; 74AHCT541-Q100

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

Transcription:

Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible with Low-power Schottky TTL (LSTTL). The provides a quad 2-input NOR function. Input levels: For 74HC02: CMOS level For 74HCT02: TTL level ESD protection: HBM JESD22-4E exceeds 2000 V MM JESD22-5- exceeds 200 V Multiple package options Specified from 40 C to +5 C and from 40 C to +25 C Table. Type number Ordering information Package Temperature range Name Description Version 74HC02N 40 C to +25 C DIP4 plastic dual in-line package; 4 leads (300 mil) SOT27-74HCT02N 74HC02D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width SOT0-74HCT02D 74HC02DB 40 C to +25 C SSOP4 3.9 mm plastic shrink small outline package; 4 leads; body SOT337-74HCT02DB 74HC02PW 40 C to +25 C TSSOP4 width 5.3 mm plastic thin shrink small outline package; 4 leads; SOT402-74HCT02PW 74HC02BQ 40 C to +25 C DHVQFN4 body width 4.4 mm plastic dual in-line compatible thermal enhanced very SOT762-74HCT02BQ thin quad flat package; no leads; 4 terminals; body 2.5 3 0.5 mm

4. Functional diagram 2 3 5 6 B 2 2B Y 2Y 4 2 3 5 6 4 9 2 3 3B 4 4B 3Y 4Y mna26 0 3 9 2 0 3 00aah04 B Y mna25 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5. Pinning terminal index area Y VCC 4 2 3 4Y Y 2 4 3 V CC 4Y B 2Y 3 2 4 02 4B 4 B 2Y 2 3 4 5 02 2 0 4B 4 3Y 2 2B 5 GND () 0 6 9 7 3Y 3B 2B GND 6 9 7 3B 3 GND 3 00aac920 00aac99 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration DIP4, SO4 and (T)SSOP4 Fig 5. Pin configuration DHVQFN4 5.2 Pin description Table 2. Pin description Symbol Pin Description Y to 4Y, 4, 0, 3 data output to 4 2, 5,, data input B to 4B 3, 6, 9,2 data input GND 7 ground (0 V) V CC 4 supply voltage NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 2 of 5

6. Functional description Table 3. Function table [] Input Output n nb ny L L H X H L H X L [] H = HIGH voltage level; L = LOW voltage level; X = don t care. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7 V I IK input clamping current V I < 0.5 V or V I >V CC + 0.5 V [] - ±20 m I OK output clamping current V O < 0.5 V or V O >V CC + 0.5 V [] - ±20 m I O output current 0.5 V < V O < V CC + 0.5 V - ±25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature 65 +50 C P tot total power dissipation [2] DIP4 package - 750 mw SO4, (T)SSOP4 and DHVQFN4 packages - 500 mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP4 package: P tot derates linearly with 2 mw/k above 70 C. For SO4 package: P tot derates linearly with mw/k above 70 C. For (T)SSOP4 packages: P tot derates linearly with 5.5 mw/k above 60 C. For DHVQFN4 packages: P tot derates linearly with 4.5 mw/k above 60 C.. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC02 74HCT02 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 - +25 40 - +25 C NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 3 of 5

Table 5. Recommended operating conditions continued Voltages are referenced to GND (ground = 0 V) continued Symbol Parameter Conditions 74HC02 74HCT02 Unit Min Typ Max Min Typ Max t/ V input transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/v V CC = 4.5 V -.67 39 -.67 39 ns/v V CC = 6.0 V - - 3 - - - ns/v 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +5 C 40 C to +25 C Unit 74HC02 V IH HIGH-level input voltage V IL V OH V OL I I LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current Min Typ Max Min Max Min Max V CC = 2.0 V.5.2 -.5 -.5 - V V CC = 4.5 V 3.5 2.4-3.5-3.5 - V V CC = 6.0 V 4.2 3.2-4.2-4.2 - V V CC = 2.0 V - 0. 0.5-0.5-0.5 V V CC = 4.5 V - 2..35 -.35 -.35 V V CC = 6.0 V - 2.. -. -. V V I = V IH or V IL I O = 20 µ; V CC = 2.0 V.9 2.0 -.9 -.9 - V I O = 20 µ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 20 µ; V CC = 6.0 V 5.9 6.0-5.9-5.9 - V I O = 4.0 m; V CC = 4.5 V 3.9 4.32-3.4-3.7 - V I O = 5.2 m; V CC = 6.0 V 5.4 5. - 5.34-5.2 - V V I = V IH or V IL I O = 20 µ; V CC = 2.0 V - 0 0. - 0. - 0. V I O = 20 µ; V CC = 4.5 V - 0 0. - 0. - 0. V I O = 20 µ; V CC = 6.0 V - 0 0. - 0. - 0. V I O = 4.0 m; V CC = 4.5 V - 0.5 0.26-0.33-0.4 V I O = 5.2 m; V CC = 6.0 V - 0.6 0.26-0.33-0.4 V V I = V CC or GND; V CC = 6.0 V I CC supply current V I = V CC or GND; I O =0; V CC = 6.0 V C I input capacitance - - ±0. - ± - ± µ - - 2.0-20 - 40 µ - 3.5 - - - - - pf NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 4 of 5

Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +5 C 40 C to +25 C Unit 74HCT02 V IH HIGH-level input voltage V IL LOW-level input voltage V OH HIGH-level output voltage V OL I I LOW-level output voltage input leakage current 0. Dynamic characteristics V CC = 4.5 V to 5.5 V 2.0.6-2.0-2.0 - V V CC = 4.5 V to 5.5 V -.2 0. - 0. - 0. V V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ 4.4 4.5-4.4-4.4 - V I O = 4.0 m 3.9 4.32-3.4-3.7 - V V I = V IH or V IL ; V CC = 4.5 V I O = 20 µ; V CC = 4.5 V - 0 0. - 0. - 0. V I O = 5.2 m; V CC = 6.0 V - 0.5 0.26-0.33-0.4 V V I = V CC or GND; V CC = 6.0 V I CC supply current V I = V CC or GND; I O =0; V CC = 6.0 V I CC C I additional supply current input capacitance per input pin; V I =V CC 2. V; I O =0; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V Min Typ Max Min Max Min Max - - ±0. - ± - ± µ - - 2.0-20 - 40 µ - 50 540-675 - 735 µ - 3.5 - - - - - pf Table 7. Dynamic characteristics GND=0V;C L =50pF;for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit Min Typ Max Max (5 C) Max (25 C) 74HC02 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 2.0 V - 25 90 5 35 ns V CC = 4.5 V - 9 23 27 ns V CC = 5.0 V; C L =5pF - 7 - - - ns V CC = 6.0 V - 7 5 20 23 ns t t transition time see Figure 6 [2] V CC = 2.0 V - 9 75 95 0 ns V CC = 4.5 V - 7 5 9 22 ns V CC = 6.0 V - 6 3 6 9 ns C PD power dissipation capacitance per package; V I = GND to V CC [3] - 22 - - - pf NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 5 of 5

Table 7. Dynamic characteristics GND=0V;C L =50pF;for load circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +25 C Unit 74HCT02 t pd propagation delay n, nb to ny; see Figure 6 [] V CC = 4.5 V - 9 24 29 ns V CC = 5.0 V; C L =5pF - 9 - - - ns t t transition time V CC = 4.5 V; see Figure 6 [2] - 7 5 9 22 ns C PD power dissipation capacitance [] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs.. Waveforms per package; V I = GND to V CC.5 V Min Typ Max Max (5 C) Max (25 C) [3] - 24 - - - pf V I n, nb input V M GND ny output V OH t PHL V Y V M V X t PLH V OL t THL t TLH 00aai4 Fig 6. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table. Measurement points Type Input Output V M V M V X V Y 74HC02 0.5V CC 0.5V CC 0.V CC 0.9V CC 74HCT02.3 V.3 V 0.V CC 0.9V CC NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 6 of 5

V I 90 % negative pulse GND V M 0 % t f t W V M t r V I positive pulse GND 0 % t r 90 % V M t W t f V M V CC G VI DUT VO RT CL 00aah76 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test V I t r, t f C L 74HC02 V CC 6.0 ns 5 pf, 50 pf t PLH, t PHL 74HCT02 3.0 V 6.0 ns 5 pf, 50 pf t PLH, t PHL NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 7 of 5

2. Package outline DIP4: plastic dual in-line package; 4 leads (300 mil) SOT27- D M E seating plane 2 L Z 4 e b b w M c (e ) M H pin index E 7 0 5 0 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2 () () min. max. b b c D E e e L M E M H 4.2 0.5 3.2 0.7 0.02 0.3.73.3 0.06 0.044 0.53 0.3 0.02 0.05 0.36 0.23 0.04 0.009 9.50.55 0.77 0.73 6.4 6.20 0.26 0.24 2.54 7.62 0. 0.3 3.60 3.05 0.4 0.2.25 7.0 0.32 0.3 0.0.3 0.39 0.33 w 0.254 0.0 () Z max. 2.2 0.07 Note. Plastic or metal protrusions of 0.25 mm (0.0 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-050G04 MO-00 SC-50-4 99-2-27 03-02-3 Fig. Package outline SOT27- (DIP4) NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 of 5

SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT0- D E X c y H E v M Z 4 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max..75 2 3 b p c D () E () e H () E L L p Q v w y Z 0.25 0.0 0.069 0.00 0.004.45.25 0.057 0.049 0.25 0.0 0.49 0.36 0.09 0.04 0.25 0.9 0.000 0.0075.75.55 0.35 0.34 Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included. 4.0 3. 0.6 0.5.27 0.05 6.2 5. 0.244 0.22.05 0.04.0 0.4 0.039 0.06 0.7 0.6 0.02 0.024 0.25 0.25 0. 0.0 0.0 0.004 θ 0.7 0.3 o o 0.02 0 0.02 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT0-076E06 MS-02 99-2-27 03-02-9 Fig 9. Package outline SOT0- (SO4) NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 9 of 5

SSOP4: plastic shrink small outline package; 4 leads; body width 5.3 mm SOT337- D E X c y H E v M Z 4 Q 2 ( ) 3 pin index 7 L detail X L p θ e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E () e H E L L p Q v w y Z() max. mm 2 0.2 0.05.0.65 0.25 0.3 0.25 0.20 0.09 6.4 6.0 5.4 5.2 7.9.03 0.9 0.65.25 0.2 7.6 0.63 0.7 0.3 0..4 0.9 θ o o 0 Note. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337- MO-50 99-2-27 03-02-9 Fig 0. Package outline SOT337- (SSOP4) NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 0 of 5

TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 pin index 2 Q ( ) 3 θ 7 e b p w M L detail X L p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm. 0.5 0.05 0.95 0.0 0.25 0.30 0.9 0.2 0. 5. 4.9 4.5 4.3 0.65 6.6 6.2 0.75 0.50 0.4 0.3 0.2 0.3 0. 0.72 0.3 θ o o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE 99-2-27 03-02- Fig. Package outline SOT402- (TSSOP4) NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 of 5

DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.5 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e 4 3 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm 0.05 0.00 0.30 0. 0.2 3. 2.9.65.35 2.6 2.4.5 0.5 0.5 2 0.5 0.3 0. 0.05 0.05 0. Note. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762- - - - MO-24 - - - EUROPEN PROJECTION ISSUE DTE 02-0-7 03-0-27 Fig 2. Package outline SOT762- (DHVQFN4) NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 2 of 5

3. bbreviations Table 0. cronym CMOS DUT ESD HBM LSTTL MM TTL bbreviations Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes 20009 Product data sheet - 74HC_HCT02_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. dded type numbers 74HC02BQ and 74HCT02BQ (DHVQFN4 package) 74HC_HCT02_CNV_2 997027 Product specification - - NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 3 of 5

5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 5.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP B.V. 200. ll rights reserved. Product data sheet Rev. 03 September 200 4 of 5

7. Contents General description...................... 2 Features............................... 3 Ordering information..................... 4 Functional diagram...................... 2 5 Pinning information...................... 2 5. Pinning............................... 2 5.2 Pin description......................... 2 6 Functional description................... 3 7 Limiting values.......................... 3 Recommended operating conditions........ 3 9 Static characteristics..................... 4 0 Dynamic characteristics.................. 5 Waveforms............................. 6 2 Package outline......................... 3 bbreviations.......................... 3 4 Revision history........................ 3 5 Legal information....................... 4 5. Data sheet status...................... 4 5.2 Definitions............................ 4 5.3 Disclaimers........................... 4 5.4 Trademarks........................... 4 6 Contact information..................... 4 7 Contents.............................. 5 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 200. ll rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: September 200 Document identifier: