EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday Sep by 5pm EE141
Today s Lecture The MOS transistor characteristics for transient analysis Propagation delay EE141 3 Review MOS Transistor Model CMOS Inverter VTC EE141 4
Important to Remember! -4 x 10.5 V S = V SAT I (A) 1.5 Linear Velocity Saturation Linear Relationship 1 0.5 V = V SAT GT V S = V GT Saturation 0 0 0.5 1 1.5.5 V S (V) Quadratic Relationship EE141 5 A Unified Model for Manual Analysis define V GT = V GS V T G for V GT 0: I =0 S B I for V GT 0: I W V min = k' VGT V L min λ ( 1+ V ) S with V min = min (V GT, V S, V SAT ) EE141 6
PMOS Load Lines Coordinate transform: I p (V Sp ) I n ( ) V in = V + V GSp I n = -I p = V + V Sp I n I p V in = 0 I n I n V in= 0 V in = 1.5 V in = 1.5 V GSp = -1 V Sp V Sp V GSp = -.5 V in = V + V GSp I n = -I p = V + V Sp EE141 7 CMOS Inverter Load Characteristics I n V in = 0 V in =.5 PMOS V in = 0.5 V in = NMOS V in = 1.5 V in = 1 V in = 1.5 V in = 1 V in = V in = 1.5 V in = 1 V in = 0.5 V in =.5 V in = 0 EE141 8
CMOS Inverter VTC.5 NMOS off PMOS res NMOS sat PMOS res 1.5 1 0.5 NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off 0.5 1 1.5.5 V in EE141 9 Inverter Gain 0 - gain -4-6 -8-10 -1 1 g = I ( V g ( V M M V kn VSATn + k p V ) λ λ Tn 1+ r V SATn n p SATp ) ( λ λ ) n p -14-16 -18 0 0.5 1 1.5.5 V (V) in EE141 10
Gain as a function of V.5 0. 0.15 (V) 1.5 1 0.5 0 0 0.5 1 1.5.5 V (V) in V in (V) (V) 0.1 0.05 Gain = -1 0 0 0.05 0.1 0.15 0. V (V) in V in (V) EE141 11 Impact of Process Variations.5 (V) 1.5 1 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS Good means: t ox L W V th 0.5 0 0 0.5 1 1.5.5 V in (V) EE141 1
Outline ynamic Operation of MOS Transistor MOS Capacitances Propagation elay EE141 13 MOS Capacitances G C GS C G S C SB C GB C B B EE141 14
The Gate Capacitance Polysilicon gate Source n + x d x d W rain n + L d Top view Gate-bulk overlap C gate ε = t ox ox WL Gate oxide t ox n + L n + Cross section EE141 15 Gate Capacitance G G G S C GC C GC C GC S S Cut-off Resistive Saturation C GCB C GCS C GC Textbook: page 109 Most important regions in digital design: saturation and cut-off EE141 16
G a t e C a p a c i t a n c e ( F ) Gate Capacitance C GC WLC ox WLC ox C GC WLC ox C GCB C GCS =C GC WLC ox C GCS C GC WLC ox 3 V GS 0 1 V S /(V GS V T ) C gate as a function of V GS (with V S = 0) C gate as a function of the degree of saturation EE141 17 Measuring the Gate Cap I V GS Capacitance (F) 10 x10-16 9 8 7 6 5 4 3 - -1.5-1 -0.5 0 0.5 1 1.5 V GS (V) EE141 18
iffusion Capacitance Channel-stop implant N A + W Bottom Side wall Source N x j Side wall L S Channel Substrate N A C diff = C bottom + C sw = C j AREA + C jsw PERIMETER = C j L S W + C jsw (L S + W) EE141 19 Junction Capacitance C j C j0 ( 1 V φ0 = m = 0.5: abrupt junction m m = 0.33: linear junction ) EE141 0
Linearizing the Junction Cap Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest C eq = Q V j Q j ( v = V high high ) Q V j ( V low low ) = K eq C j0 K eq = ( V high φ V 1 m 1 m [( φ V ) ( φ V ] m 0 0 high 0 low low) (1 m) ) EE141 1 Capacitive evice Model G C gate = C GB + C GS + C G C GS C G = C GCS + C GSO = C GC + C GO S C SB C GB C B = C diff = C GCB = C diff B EE141
Capacitances in 0.5µm CMOS Process Textbook: page 11 EE141 3.MOEL Parameters MOS1.MOEL Modname NMOS/PMOS <VT0=VT0 > EE141 4
Two Inverters V PMOS In Out 1.µm =λ Metal1 Polysilicon NMOS GN EE141 5 Two Inverters (modern view) V EE141 6
Computing the Capacitances V V M C db C g4 M4 V in C gd1 M1 C db1 C w C g3 M3 Simplified Model V in C L Fanout EE141 7 The CMOS Inverter: C in S C gsp C in V in G C gdn,p C L C gsn S EE141 8
Miller Effect Z F i 1 = V in (1-A) Z F i 1 V in A Z L i 1 = V in Z 1 V in i 1 A Z 1 Z Z L EE141 9 Miller Effect Z F A A Z 1 Z Z 1 = Z F 1 A Z = Z F 1 A 1 C 1 = C F (1 A) C 1 = C F (1 1/A) EE141 30
CMOS Inverter Example: C in C gsp C gs = C gsn + C gsp + V C gd - V C gd = C gdn + C gdp C in A = -1 C gsn C in = C gs + C gd (1-A) EE141 31 The Miller Effect V C gd1 V V in V C gd1 C gd1 M1 V V in M1 A capacitor experiencing identical but opposite voltage swing at both terminals can be replaced by a capacitor to ground, whose value is two times the original value EE141 3
Computing the Capacitances V V M C db C g4 M4 V in C gd1 M1 C db1 C w C g3 M3 Simplified Model V in C L Fanout EE141 33 Computing the Capacitances EE141 34
Outline ynamic Operation of MOS Transistor MOS Capacitances Propagation elay EE141 35 CMOS Inverter Propagation elay: Approach 1 V t phl C = L V I swing avg I avg C L t phl CL ~ k V n V in = V EE141 36
CMOS Inverter Propagation elay: Approach V t phl = f ( R C ) L on = 0. 69R C on L ln(0.5) C L 1 V R n 0.5 0.36 V in = V R on C L t EE141 37 MOS Transistor as a Switch V GS V T Traversed path S R on I V GS = V R mid R 0 V / V V S R R t t t 1 1 VS eq = avg( Ron( t)) = R ( ) = = on t dt t t1 t t1 t ) t1 t1 I t1 1 ( R ( t ) R ( )) eq on 1 + on t ( t) dt ( t EE141 38
The Transistor as a Switch V GS V T I V GS = V R on S R mid R 1 = ( R R ) eq mid + 0 R 0 V / V V S R R eq eq 1 = I 3 V 4 I SAT SAT V + ( 1+ λ V ) ( 1+ ) I SAT λ V 5 1 λ V 6 V EE141 39 Transient Response 3.5? t p = 0.69 C L (R eqn +R eqp )/ (V) 1.5 1 t plh t phl 0.5 0-0.5 0 0.5 1 1.5.5 t (sec) x 10-10 EE141 40
esign for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase V (?) EE141 41 elay as a function of V 5.5 5 t p (normalized) 4.5 4 3.5 3.5 t phl 3 CL V = 0.69 4 I SATn R eq = 0.5 ( W L) k ' V n n SATn CL V ( V V Tn V SATn ) 1.5 1 0.8 1 1. 1.4 1.6 1.8..4 V (V) EE141 4
evice Sizing 3.8 x 10-11 3.6 (fixed load) t p (sec) 3.4 3. 3.8.6.4. Self-loading effect: Intrinsic capacitances dominate 4 6 8 10 1 14 S EE141 43 NMOS/PMOS Ratio 5 x 10-11 tplh tphl 4.5 t p (sec) 4 tp β = W p /W n 3.5 3 1 1.5.5 3 3.5 4 4.5 5 β EE141 44
Impact of Rise Time on elay 0.35 0.3 t phl (nsec) 0.5 0. 0.15 0 0. 0.4 0.6 t rise (nsec) 0.8 1 t p = t step(i) + η t step(i-1) EE141 45 The Sub-Micron MOS Transistor Threshold Variations Sub-threshold Conduction Parasitic Resistances EE141 46
Threshold Variations V T V T Long-channel threshold Low V S threshold L V S Threshold as a function of channel length (for low V S ) rain induced barrier lowering (IBL) (for low L) EE141 47 Sub-Threshold Conduction I (A) 10-10 -4 10-6 10-8 Quadratic Linear The Slope Factor I ~ I 0 e qvgs nkt, C n =1+ C S is V GS for I /I 1 =10 ox 10-10 Exponential 10-1 V T 0 0.5 1 1.5.5 V GS (V) Typical values for S: 60 100 mv/decade EE141 48
Sub-Threshold I vs. V GS qvgs nkt I I0e 1 e qvs = kt I V S from 0 to 0.5V V GS EE141 49 Sub-Threshold I vs. V S I qvgs qvs = nkt kt I e 0 1 e ( 1+ λ V ) S I V GS from 0 to 0.3V V S EE141 50
Next Lecture Optimizing for Performance Power dissipation in CMOS inverters EE141 51