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UNIVERSITI TUNKU ABDUL RAHMAN Semiconductor Technologies Quality Control Dr. Lim Soo King 1/2/212

Chapter 1 Quality Control... 1 1. Introduction... 1 1.1 In-Process Quality Control and Incoming Quality Control... 1 1.2 Statistical Process Control... 2 1.2.1 Establishing Statistical Control Chart for Process Mean... 4 1.2.2 Establishing Statistical Control Chart for Process Standard Deviation... 6 1.2.3 Establishing Statistical Control Chart for X and R Charts... 8 1.2.4 Special Charts... 8 1.3 Process Capability Ratio and Process Capability Index... 14 1.3.1 Process Capability Ratio C p... 14 1.3.2 Process Capability Index C pk... 16 1.3.3 Taguchi Process Capability Index C pm... 18 1.3.4 P pk Index... 19 1.4 Reliability... 21 1.4.1 Failure Rate... 22 1.4.2 Mathematics of Failure and Reliability Functions... 23 1.4.3 Distribution Function of Failure Rate... 25 1.4.4 Accelerated Testing... 27 Exercises... 3 Answers of Exercises... 32 Bibliography... 34 - ii -

Figure 1.1: Data collected for the hermetic lid length at incoming store room... 5 Figure 1.2: Statistical control chart of the data shown in Fig. 1.1 using X and R as estimate... 5 Figure 1.3: Statistical control chart of the data shown in Fig. 1.1 using X and s as estimate... 6 Figure 1.4: A pre-control chart... 9 Figure 1.5: Data for D-NOM chart... 1 Figure 1.6: Data for standardized X and R charts... 12 Figure 1.7: Control chart of standardized mean X... 13 Figure 1.8: Control chart of standardized range R... 13 Figure 1.9: Processes with same C pk but different C pm indices... 19 Figure 1.1: Failure rate versus time for a typical integrated circuit... 25 - iii -

Chapter 1 Quality Control 1. Introduction In integrated circuit manufacturing involves design, fabrication, assembly, and test processes. To ensure that each process step conforms to specifications, it is necessary to implement quality control scheme. Quality control monitoring/checking has become an important process and is normally imposed at the end of certain critical process steps. Besides the quality control at in process step, quality control procedure is also required to be implemented at the incoming material inspection stage. With the quality control in place at critical process steps and at incoming material acceptance stage, it is also necessary to monitor the process stability/reliability and process capability of the machine/equipment used to process the device. In this section, student will learn how in process quality control and incoming control are performed. The concepts of how to establish statistical process control charts and at the same time learn how use the collect data to determine the process capability ratio C P and process capability index C PK of the machine/equipment used for the manufacturing processes. At the last of learning, the concepts and methods used to determine the reliability of integrated circuit are studied. 1.1 In-Process Quality Control and Incoming Quality Control In-process quality monitoring/inspection always helps to check and balance if the device is manufactured according to the specifications and if the operator processes the device according to the operational procedure. Normally the samples according to a specific sampling plan (usually.25 AQL sampling plan) are pull from a process lot/batch at the end of critical process step such as die attach, wire bonding, initial/final tests at temperature. If there is any failure detected, non-conformance notice is normally issued to manufacturing line manager for taking necessary collective actions. After the corrective action has - 1 -

been taken, quality control personnel will take new samples to check for conformance to specifications. When conformance is achieved, the particular process is then released to manufacturing for further processing of device. The failed sample lot is either re-processed or declared as total reject. Let s take a critical process step, which is wire bonding. After wire bonding process, the quality control personnel will pull the samples according to specific quality sampling plan to check the wire loop height and wire bond strength according to specifications. Besides, he/she also checks if there is missing wire, bond crack, wrong bonding etc. If there is any non-conformance detected, stop process notice is issued. The process will only be allowed after collective action has been taken and the subsequent samples pass the quality control check/test. In test operating, the quality control personnel would pick the sample according to the quality sampling plan to test to see if all selected samples pass the electrical test specifications. If selected samples fail the sampling plan, the tested lot is normally re-tested and re-submitted for sampling test. At incoming inspection, the quality control personnel will pull samples from the incoming materials like the hermetic package lid to check if the dimensions, strength of the material etc. meeting the specifications. If the samples fail the sampling plan, the batch of hermetic lids is return to vendor. 1.2 Statistical Process Control In the aspects to monitor the process stability, it is necessary to set-up statistical process control chart SPC to monitor the repeatability and reproducibility of the process to monitor if there is variation due to machine, time factor, operator factor, environmental factor etc. Let s take the case wire bonding operation, the bond strength in gram-force and height of wire loop in mm can be plotted on control charts at specified interval to the check the trends of the bond strength and height of wire loop. If there is abnormal deviation from the targeted values as well as their distribution variation over a period of the time, analysis can be done. Since the data is taken real time in the manufacturing line, any deviation from the pre-specified control limits would immediately alert the operator to find the underlying causes and correct the problem before large amount nonconformance or defective devices are produced. Comparison of SPC charts can also be done to check for variations between machines particularly this case the wire bonding machines. - 2 -

Any conformance manufacturing process, over a period of time process 2 data has mean value and variance value. Thus, one can say these data values are in control since the process is a conformance process. It is important 2 and desires that the mean and variance of the subsequent process distribution throughout the entire duration of the process remains equal to 2 and irrespective of time and duration. To continuous ensuring = 2 2 and, it requires continuous monitoring by an easier mean of establishing the statistical control chart SPC. Statistical speaking, it is the testing of hypothesis that is the null hypothesis H : = and H : versus the alternative hypothesis, which is H 1 : and H 1 :. If both null hypotheses are true, one says that the process is in control. If either one or both are not true then the process is out of control. When setting up a hypothesis testing for the mean, one considers the null hypothesis = versus the alternative hypothesis, selecting an unbiased statistic with minimum variance as possible, which means x, specify probability of Type I error, which is = P[Rejecting H, when it is true], and using and distribution of x to set-up acceptance region for x that is accept the null hypothesis H if Z / 2 / n < x < Z / 2 / n and reject the null hypothesis H if x < / n or x > / n. Z / 2 Z / 2 The statistical control chart has three lines, which are upper control limit line UCL, center line CL, and lower control limit line LCL. These lines are established based on the data collected over a period of time from a normal conformance process and in the control acceptance region mentioned in the above paragraphs. Thus, the upper control limit UCL line is defined as UCL = / n (1.1) Z / 2 The lower control limit LCL line is LCL = / n (1.2) Z / 2 The center line CL is CL = (1.3) - 3 -

where n is equal to number of sample. is probability of accepting the null hypothesis when it is actually not true. The value of is taken as.26, which means that the 99.74% of the distribution is in the acceptable region. Z /2 is z- score for the two-tailed standard normal distribution function, which has a value 3. for =.26. Based on these statistical values, equation (1.1) and (1.2) will become UCL = / n (1.4) 3 The lower control limit LCL line is LCL = / n (1.5) 3 The type II error will not be discussed here, where it defines equals to the probability of the accepting the null hypothesis when actually it is not true. Once the control chart is established and in used. If the trend of chart has any of the following stated abnormality, collective action must be taken for the specific process. The rules Seven points in a row on one side of the center line. Seven points in a row consistently going up or coming down. Substantially more than 2/3 of the points close to the center line. Substantially less than 2/3 of the points close to the center line. 1.2.1 Establishing Statistical Control Chart for Process Mean Presented in this section are two ways to established the statistical control chart SPC for process mean X using X, R /d 2, and s /c 4. 1.2.1.1 Estimating by X and by R /d 2 Let s use the data shown in Fig. 1.1 to illustrate how and can be estimated by the mean X of the sample at defined interval and the range R of the sample to estimate the value of. - 4 -

Batch # Sample 1 x 1 Sample 2 x 2 Sample 3 x 3 Sample Mean X Range R 1 Quality Control Standard Deviation or s 1 4.5 4.6 4.5 4.53.1.6 2 4.6 4.5 4.4 4.5.2.1 3 4.6 4.5 4.4 4.5.2.1 4 4.4 4.6 4.4 4.47.1.12 5 4.3 4.5 4.4 4.4.1.1 Average X = 4.48 R =.18 or s =.95 = 4.48 and =.94 Figure 1.1: Data collected for the hermetic lid length at incoming store room Let X be the grand average of the mean X for five batches of hermetic lid length and R be the grand average of the range R for five batches of hermetic lid length. The mean can then be estimated by X and the standard deviation ( ) is estimated by R /d 2, whereby the value of d 2 can be obtained from the constant table (refer to Appendix B) used for estimation and construction of control chart. For the sample size of n = 3, d 2 value is 1.6929. Thus, the established lines of the control chart are: UCL = 3R /(d n) = X 2 4.48 3x.18/(1.6929 3) = 4.66, LCL = 3R /(d n) = 4.48 3x.18/(1.6929 3) = 4.29, and CL = 4.48. X 2 The plot of the established statistical control chart is shown in Fig. 1.2. Figure 1.2: Statistical control chart of the data shown in Fig. 1.1 using X and R as estimate - 5 -

1.2.1.2 Estimating by X and by s /c 4 Let or s be the grand average of the standard deviation then the standard deviation is estimated by /c 4, whereby the value of c 4 can be obtained from the constant table used for estimation and construction of control chart. For the sample size of n = 3, c 4 value is.9213. Thus, the established lines of the control chart are: UCL = 3 /(c n) = 4.48 3x.95/(.9213 3) = 4.65, LCL = X 4 X 4 3 /(c n) =.48 3x.95/(.9213 3) 4 = 4.3, and CL = 4.48. The plot of the established statistical control chart is shown in Fig. 1.3. Figure 1.3: Statistical control chart of the data shown in Fig. 1.1 using X and s as estimate 1.2.2 Establishing Statistical Control Chart for Process Standard Deviation Presented in this section are two ways to established the statistical control chart SPC for process standard deviation s using R /d 2, and s /c 4 statistics. The lengthy discussion of how to establish the statistical control chart using these two statistics will not be described. 1.2.2.1 Using R /d 2 Statistics - 6 -

The formulae for the lines of the control chart for process standard deviation established using R /d 2 statistics are LCL = 3d /d R = D 3 R (1.6) UCL = 1 3 2 3d /d R = R 1 3 2 D 4 (1.7) CL = R (1.8) The values of d 2, d 3, D 3, and D 4 can be obtained from the constant table (refer to appendices) used for estimation and construction of control chart. For the sample size of n = 3, d 2 = 1.6929, d 3 =.8884, D 3 =, and D 4 = 2.5743. One may ask; why D 3 is equal instead of -.5743. The reason being the standard deviation cannot be a smaller than. Using data shown in Fig. 2.19, the lines of the control chart are: LCL = 1 3d 3 /d2 R =, UCL = 1 3d 3 /d2 R =.4639, and CL = R =.18. 1.2.2.2 Using s /c 4 Statistics The formulae for the lines of the control chart for process standard device established using s /c 4 statistics are LCL = UCL = 3 1 c 4 1 s = s c 4 3 1 c 4 1 s = s c 4 B 3 (1.1) B 4 (1.11) CL = s (1.12) The values of c 4, B 3, and B 4 can be obtained from the constant table used for estimation and construction of control chart. For the sample size of n = 3, c 4 =.8862, B 3 =, and B 4 = 2.5684. One may ask why B 3 is equal instead of -.14198. The reason being the standard deviation cannot be a smaller than. Using data shown in Fig. 1.1, the lines of the control chart are: LCL = 3 1 c 4 1 s = s c 4 3 1 c = s c 4 4 B 3 =, UCL = 1 s B 4 =.244, and CL = s =.95. - 7 -

1.2.3 Establishing Statistical Control Chart for X and R Charts X chart is meant for individual measurement and R chart is meant for moving range. The sample taken at designated interval is one not like the earlier case that has more than one. The acceptable control limits of the process mean X is 3 / n = 3 R / d 2 n taking is equal to.26. Since for individual measurement n = 1, then the for formulae for the lines of control chart are LCL X 3R / (1.13) d 2 CL = X (1.14) UCL (1.15) X 3R /d 2 Since moving range is calculated from two successive data, thus, d 2 is equal to 1.128 taken from the constant table used for estimation and construction of control chart. The formulae for the lines of control charts are: LCL X 3R / d 2 X 2.66R, CL = X, and UCL X 3R /d2 X 2.66R. The formulae for the statistical control chart for moving range R chart with assumption that is equal to.26 are LCL D3R (1.16) CL = R (1.17) UCL D4 R (1.18) From the constant table used for estimation and construction of control chart, D 3 = and D 4 = 3.2672. Thus, the formulae for the moving range R control charts are; LCL, CL = R, and UCL 3.267R. 1.2.4 Special Charts There are situations where it may be difficult to take a sample of size greater than one or when only one measurement is meaningful each time. Some examples of these situation are the production rate is very slow or the batch size is very small or a continuous process such as chemical process, measurement on - 8 -

some quality characteristics, such as viscosity of paint or thickness of insulation on a cable, varies only a little between successive observations. Based on these examples, it is difficult to establish SPC charts like those discussed earlier. Let s discuss a few methods to overcome these situations. 1.2.4.1 Pre-Control Chart Individual measurement is plotted on this chart. This is suitable for situation where the size of a batch is small. The control limits are established based on the specification limits. As an example, let the specification limits for a quality characteristic be.5±.2, which means LSL =.498 and USL =.52. The center line of the chart is located at the nominal size of.5. Horizontal lines are drawn at the upper specification limit of.52) and the lower specification limit of.498. In addition, horizontal lines are also drawn at nominal size ±1/4 (USL LSL). In this example, these lines are at.5 1/4x(.52.498) =.499 and.5 + 1/4x(.52.498) =.51. The regions above the USL and below the LSL are called the red zone, the interval between nominal size 1/4 x total tolerance and nominal size + 1/4 x total tolerance is called the green zone, and the regions between the red and green zones are called the yellow zone. The control chart is shown in Fig. 1.4. Figure 1.4: A pre-control chart The following rules are used while setting up the process: 1. Collect the measurements and plot them on the chart until five consecutive values fall in the green zone. - 9 -

2. If a measurement data falls in the yellow zone, restart the count to obtain five consecutive pieces in the green zone. Do not adjust the process. 3. If two consecutive data fall in the yellow zone or one value falls in the red zone then adjust the process. 4. When five consecutive measurement data fall in the green zone, approves the setup as in-control process and starts regular manufacturing. During regular manufacturing, sample two consecutive components every h interval such as 1 minutes and follow these rules: 1. If the first data falls in the green zone, do not plot the second value and continue the process. 2. If the first data falls in the red zone, stop the process and investigate. 3. If the first data falls in the yellow zone, then plot the second value. If it falls in the green zone then continue the process, otherwise, stop the process and investigate. This chart is simple to maintain, which is very important. One main disadvantage is that the information presented by the chart regarding the variability of the process is incomplete. 1.2.4.2 D-NOM Charts In these charts, the deviations of the characteristics from their respective nominal values are used as the observations. The calculations of the control limits are done in the same manner as in the regular X and R charts. Let s use the data shown in Fig. 1.5 to establish D-NOM charts. The nominal values of two parts are 3. and 2. respectively were produced using an equipment. Batch Part Obs 1 Obs 2 Obs 3 Dev. of Obs 1 x i from nominal value Dev. of Obs 2 x i from nominal value Dev. of Obs 3 x i from nominal value Test Statistics x Test Statistics R 1 A 3 31 32 1 2 1. 2 2 A 29 3 31-1 1. 2 3 A 28 29 32-2 -1 2 -.33 4 4 B 2 22 21 2 1 -.67 2 5 B 2 22 19 2-1.33 2 6 B 22 21 18 2 1-2.33 4 7 B 2 19 18-1 -2-1. 2 8 B 19 2 2-1 -.33 1 X =.84 Figure 1.5: Data for D-NOM chart - 1 - R = 2.375

D-NOM charts are established based on the assumptions that the process standard deviation is the same for all parts and sample size is constant. The control limits of the established are X and R charts are as follows: X chart UCL = LCL = X 2 A R (1.19) X 2 A R (1.2) CL = X (1.21) From Appendix B, A 2 is equal to 1.231 for sample size n = 3. R chart UCL = LCL = D 4 R (1.22) D 3 R = (1.23) CL = R (1.24) From Appendix B, D 3 is equal to and D 4 is equal to 2.575 for n = 3. 1.2.4.3 Standardized X and R Charts These charts are used if the assumption that the standard deviation is not the For the part type j test statistic, let X j be the target value for part type j and R j be the average range of part type j then where j X j X chart test statistics = j j j x is equal to x ij Xj/ n n i1 test statistics is also equal to ij / R j standardized X shall be x X / R = (1.25) - 11 - and n is the sample size. The X chart x if X j is equal to zero. The control limits of LCL = -A 2 (1.26)

UCL = A 2 (1.27) CL =. (1.28) The R chart test statistic is equal to R R / R and the control limits are ij j LCL = D 3 (1.29) UCL = D 4 (1.3) CL = 1. (1.31) Let s now use the data shown in Fig. 1.5 to establish standardized X and R charts. Batch Part Dev. of Obs 1 x i Dev. of Obs 2 x i Dev. of Obs 3 x i x j R j Test Statistics x Test Statistics R 1 A 1 2 1. 2 1/2.67 =.375 2/2.67 =.75 2 A -1 1. 2. 2/2.67 =.75 3 A -2-1 2 -.33 4 -.33/2.67 = -.124 4/2.67 = 1.5 R 2.67 4 B 2 1.67 2.67/2.2 =.35 2/2.2 =.99 5 B 2-1.33 2.33/2.2 =.15 2/2.2 =.99 6 B 2 1-2.33 4.33/2.2 =.15 4/2.2 = 1.818 7 B -1-2 -1. 2 1./2.2 = -.455 2/2.2 =.99 8 B -1 -.33 1 -.33/2.2 = -.15 1/2,2 =.455 R 2.2 Figure 1.6: Data for standardized X and R charts The control limits of standardized X and R charts are: Standardized X ; LCL = -1.23 for n = 3, UCL = 1.23, and CL =.. R chart; LCL =, UCL = 2.575 for n = 3, and CL = 1.. The control charts are respectively shown in Fig. 1.7 and 1.8. - 12 -

Standardized Mean Chart 1.5 1.5 -.5 1 2 3 4 5 6 7 8 Mean LCL CL UCL -1-1.5 Observation Figure 1.7: Control chart of standardized mean X Standardized R Chart 3 2.5 2 1.5 1 R LCL CL UCL.5 1 2 3 4 5 6 7 8 Observation Figure 1.8: Control chart of standardized range R - 13 -

1.3 Process Capability Ratio and Process Capability Index Process capability ratio C P or capability index C pk allows process engineer and quality control engineer to determine ability of the machine/equipment performing certain process. Using the example for the case of wire bonding, if the specification of bond strength is 5g±5g, which shall mean the lower specification limit LSL is 45g and upper specification limit USL is 55g. If the average measurement for the samples taken from a specific wire bonder is 53g, we would like to say this wire bond has poor capability index C pk. Likewise, the average measurement for the second wire bonder is 5.3g, we say this wire bonder has better process capability index C pk then the previous wire bonder. Let s go through the process of establishing process capability ratio C p, process capability index C pk, and Taguchi process capability index C pm for the machine/equipment. 1.3.1 Process Capability Ratio C p Process capability is simply the range that contains all possible values of a specified quality characteristics generated by a process under a given set of conditions. For a normal distribution with α =.26, the range shall contain 99.74% of the values, which is equal to six standard deviation (). Thus, the process capability is Process capability = 6 (1.32) The recent trend for the process capability is looking at eight standard deviations, which is 99.9937% or 12 standard deviations, which is 99.9999998% of the values covering in the range. Process capability ratio C p compares the specification limits of the characteristics of the device with the process capability. Thus, process capability ratio C p is defined as C p = USL LSL 6 (1.33) where LSL is the lower specification limit and USL is the upper specification limit. For the VLSI device process, it normally demands the process capability ratio of more than 2, which means C p 2. - 14 -

The portion of out of specification device produced is P[X < LSL] + P[X > USL], which either equal to 2xP[X < LSL] or 2xP[X > USL]. If the mean of the device produced is = (USL+LSL)/2, then the probability of defective device is 2 P z LSL LSL (USL LSL) / 2 = 2P z or 2 P z USL = USL (USL LSL) / 2 P z 2, where z = (X-)/ that has standard normal distribution with mean equals to and standard deviation equals to 1. After substituting from equation (1.33), the portion of defective device is equal to or Pz 2P z 3C p 3C p 2 (1.34) For the case whereby there only one specification limit, which is either LSL or USL, the process capability ratio are respectively equal to C p = ( LSL) 3 for the larger the better characteristic (1.35) C p = (USL ) 3 for the smaller the better characteristic (1.36) The portion of out of specification device produced is P[X < LSL] or P[X > USL], which are also equal to P z LSL or P z USL. After substituting equation (1.35) and (1.36), the out of specification device portions are respectively equal to P z 3C p - 15 - for the larger the better characteristic (1.37) P z 3C p for the smaller the better characteristic (1.38) For the process case whereby the process mean is not equal to = (USL- LSL)/2, which shall mean that can either closed to LSL or USL, the portion of the defective device produced is equal to P z LSL + P z USL (1.39) Let s take an example to illustrate how equation (1.39) works. In test operation, three testers are used to measure the leakage current for a batch of

devices. The specification of the leakage test is ±3.nA. The means obtained from three testers are 2nA, 1nA, -15nA, while the standard deviations obtained from three testers are 5.nA, 6.nA and 4.nA respectively. Find the portion of defective devices produced by the three testers. With known z-score, use the standard normal cumulate probability table to obtain the cumulative probability of reject. The LSL is -3nA, while the USL is 3nA. The portion of defective device produced by tester 1 is P z LSL + P z USL 3 2 3 2 = P z + P z = P[z < -1] + P[z > 2] = 1-.9772 =.228. The portion of defective device produced by tester 2 is 3 1 z LSL P + P z USL = 5 P z 6 + P z = P[z<-6.67]+P[z>3.33] = 1-.9995 =.5. The portion of defective device produced by tester 3 is 3 15 z LSL P + P z USL = P z 4 + P z = P[z<-3.75]+P[z>11.25] = 1-.9999 =.1. 5 3 1 6 3 15 4 Based on the example shown above, one can see that tester 3 is the most capable tester. One can also see that the deviation of the mean from the nominal value (in this case is na) has greatly affect the portion of the defective device produced by the testers. This effect is not capture by the process capability ratio (C p ) because this ratio always assumes that the mean of the process is always equal to (USL+LSL)/2. We shall discuss a different way that is to calculate the process capability index C pk to identify the effect. 1.3.2 Process Capability Index C pk Process capability index C pk is introduced to resolve the limitation of process capability ratio C p. From the example shown above, the mean of tester 1 is closer to the LSL, which means (USL - ) < ( - LSL). The mean of tester 2 is closer to USL, which means (USL - ) < ( - LSL). The mean of tester 3 is closer to LSL, which means ( - LSL) < (USL - ). Thus, there are two testers have their means closed to LSL. The question is between the two testers, which one has a better capability index? - 16 -

Based on the above example, this shall mean that the process capability ratio C p shall be taken from the value closer to either the LSL or USL divided by a divisor, which should be 3 instead of 6 because it does not cover the entire range of the specifications. Thus, the process capability index C pk is defined in equation (1.4) the device characteristics that have both LSL and USL limits. LSL USL C pk Min, (1.4) 3 3 The process capability index C pk for VLSI device process demands the index value of at least 1.5. i.e. C pk 1.5. For the device characteristic that has either LSL or USL, the process capability index C pk is defined as C pk = ( LSL) 3 for the larger the better characteristic (1.41) C pk = (USL ) 3 for the smaller the better characteristic (1.42) Let s use the earlier example to calculate the process capability indices of the LSL USL three tester s. The C pk of tester 1 is C pk Min, = = 3 2 =.6666. The C pk of tester 2 is USL 3 3x5 LSL USL Min, 3 3 LSL USL Min, 3 3 C pk = USL is 3 3 C pk = - 17-3 3 = 3 1 = 1.1111. The C pk of tester 3 3x6 LSL = 3 1 3x4 = 1.6666. Based on the results, one can clearly see that tester 3 has a better process capability index then two other two testers and tester 1 has the least process capability index. These results concur with portion of defective device produced by the testers using C p method. The portion of out of specification device produced is P[X < LSL] + P[X > LSL USL USL] = P z P z. If the mean is closed to LSL then LSL USL P z P z and C pk = ( LSL) 3, this shall mean that

portion of the defective device can be approximately as 2 times P z LSL i.e. 2 P z LSL. Replacing the mean µ using equation (1.41), the portion of the defective device is equal to P z LSL 2 = 2Pz (1.43) 3C pk Similarly, if the mean is closed to USL, then and C pk = (USL ) 3 approximately as 2 times P z LSL USL P z. This shall mean that portion of the defective device can be P z LSL i.e. 2 P z LSL. Replacing the mean µ using equation (1.42), the portion of the defective device is equal to P z USL 2 = Pz 3C pk 2 (1.44) The main limitation of the C pk index is due to the normality assumption of the characteristics. Also, for the nominal-the-better type of characteristics, the C pk index yields only an upper bound for the total proportion of defectives. 1.3.3 Taguchi Process Capability Index C pm Taguchi process capability index C pm takes into the consideration of loss due to variation from the targeted value by replacing the standard deviation of the 2 process capability index C p with the Taguchi s loss function X 2, where X is the targeted value. It is useful to identify processes that have same C pk. The C pm index is calculated using equation (1.45). C pm = USL LSL 2 6 X 2 (1.45) Let s use the example shown in Fig. 1.9 as the illustration. The targeted value of the process is 1.. The two processes have same C pk values but different C pm indices theoretically saying that process B has a better process capability. In practice, it may not be true since the variance of process B is higher means expected more dissatisfaction from end user. The C p values of process A and B are respectively equal to 1.389 and.833, while the C pk values are both equal to - 18 -

.833. Although process A has lower standard deviation, its mean is further away from target value. This resulted same C pk value like the process B whereby it has wider spread with mean closes to target value. Figure 1.9: Processes with same C pk but different C pm indices The calculated C pm for the processes are.712 for process A and.833 for process B. 1.3.4 P pk Index Wrong estimation of mean and standard deviation was shown as one source of error in measuring the process capability. Let s take an example. 5 observations collected over a period of 6 minutes. These observations were collected in 1 sample batches of size 5 each. The time interval between successive batches was 1 minutes. The following estimates of the process standard deviation were obtained. 1. Average value of standard deviations of the 1 sample batches is.738. 2. Standard deviation of the entire 5 observations taken as one sample batch is.1329. It was pointed out that the estimate given by.738 contains the variation within each sample batch of size 1 (short-term variability) only, whereas the estimate of.1329 contains the variation within the batches as well as the long-term variation in the process over a period of 6 minutes. Assuming that the process was not stopped and adjusted during the interval of 6 i.e. the - 19 -

process control technique used to monitor the process allowed the observed deviation in the mean. The true estimate of the total variability in the characteristic is.1329. Usually the estimate of the variation within each batch size of 1 is used in calculating of C p and C pk indices. As this estimate is smaller than the estimate of the total variation including the long-term variability, these indices over estimate the process capability and hence under estimate the proportion of defectives. In order to address this problem, the P pk index was introduced. The P pk index is calculated using the same formulae for calculating the C pk index. For nominal-the-better type of formula is LSL USL P pk Min, (1.46) 3 3 For the device characteristic that has either LSL or USL, the process capability index C pk is defined as P pk = ( LSL) 3 for the larger the better characteristic (1.47) P pk = (USL ) 3 for the smaller the better characteristic (1.48) The above formulae shown the standard deviation is estimated by long-term standard deviation. The proportion of defectives is estimated in the same manner like C pk index, which is LSL 2 P z = 2 P z USL 2P z P z = = 3P pk 3P pk For nominal-the-best type of characteristics and 2P z 2 (1.49) or Pz 3P pk 2 (1.5) 3P pk For smaller the better and larger the better types characteristics. As in the case of the C pk index, the distribution of the characteristic must be normal in order for equation (1.49) and (1.5) to be valid. - 2 -

Let s take an example to calculate the P pk index for the data that has USL.995, USL 1.5, batch average standard deviation.738, long-term standard deviation.1329, batch average mean 1.1, long-term batch mean 1.5 and estimate the proportion of defectives using the P pk index. The P pk index is calculated using equation LSL USL 1.5.995 1.5 1.5 P pk Min, Min, 3 Min1.379,1.128 3 = 1.128. 3x.1329 3x.1329 The C pk index is calculated using equation LSL USL 1.1.995 1.5 1.1 C pk Min, Min, Min2.71,1.86 = 1.86. 3 3 3x.738 The portion of reject using P pk is Pz =.8 = 8ppm. 3P pk 3x.738 2 = Pz 3x1.128 The portion of reject using C pk is Pz 2.42x1-8 =.8 =.242ppm. 3C pk 2 = 2x[1-.9996] 2 = Pz 3x1.86 2 = 2x1.21x1-8 = From the results, one can see that P pk gives a more realistic result than C pk. The limitations of the P pk index are the same as those of the C pk index discussed earlier. In short, these are the normality assumption required for the expressions to be valid, the upper bound on the proportion of defectives, and the masking of the deviation of the mean from the target value by the standard deviation. 1.4 Reliability Reliability is a study of probability that a component such as integrated circuit, equipment, or system will satisfactorily perform the intended function under given circumstances, such as environmental conditions, limitations as to operating time, and frequency, and thoroughness of maintenance, for a specified period of time. Thus, an integrated circuit designed for the operation in the space for a period of 15 years and if this integrated circuit can live up with the intended period then one can say that this integrated circuit is reliable. - 21 -

In this topic, student will learn the definition of failure rate, the statistical distribution models used to calculate the reliability function, the failure rate, and the cumulative fail function of the device/system. The student will also learn the failure rate for the lifetime of the device and the accelerated test methods used to wipe-out unreliable device earlier instead of waiting for a long time before failure is shown up under normal operation conditions. 1.4.1 Failure Rate A system such as a calculator that made of many semiconductor devices is put in operation for the purpose of calculation, would have a certain failure rate (), which means it may fail after certain number of operating hour. Thus, a calculator (system) has failure rate with respect to operating time. The question is if such failure is acceptable to end-user. Let s take another example. A certain failure rate of the system in a commercial aircraft is it acceptable to airtravelling passengers? The failure rate () of a semiconductor device implemented in the system is defined as 1Failure No of transistor x period of operation (1.51) If a system contains 1, transistors then the failure rate () from one month operation is equal to 1Failure No of transistor x period of operation 1Failure, 5 1.x1 x 72 hrs which is equal to 14x1-9 Failure/Device-hour. If the unit of failure is defined to be 1 Failure Unit = 1 FIT = 1 Failure/1 9 Device-hour then the example shown has failure rate <14 FIT. If one now considers a system that has 225 integrated circuits and the failure rate of integrated circuit is 1 FIT. One can calculate the mean time to a failure using equation (1.51). Thus, 1Failure 225 x 1x1 = -9 1Failure Period of operation No of transistor x = 4.44x1 4 hrs, which is equal to 5.13 years. The percentage of failure per month shall be 1x1-9 x225x72x1% = 1.62%. - 22 -

1.4.2 Mathematics of Failure and Reliability Functions 1 Quality Control Based on the above discussed example, one would see that it is time consuming before a failure is shown out. We cannot be waiting for 5.13 years to see a failure is shown out to calculate the failure rate of a system. One ought to have a developed method by sample testing to predict the failure rate of the system. In this section, it discusses the methods to quantitatively measure and predict device failure rate, and to identify and eliminate the failure mechanism. If a device or system is operating at time t =. The probability that the device will fail at or before time t is given by the function F(t). This is a cumulative distribution function (cdf) with the following properties. F(t) = t < F(t) F(t ) t t (1.52) F(t) 1 t The reliability function R(t) is a probability that the device will survive to time t without failure. Thus, the reliability function R(t) is related to fail function by equation (1.52). R(t) = 1- F(t) (1.52) The derivative of fail function F(t) with respect to time is known as the probability density function (pdf) and is represented by f(t). Thus, the pdf is related to the cdf by d ( t) F(t) dt or the cumulative function f (1.53) F(t) f (x)dx (1.54) t Similarly the reliability function, t R(t) f (x)dx (1.55) and - 23 -

d ( t) R(t) dt f (1.56) In most applications, the most concern is the hazard rate, which is referring to instantaneous failure rate. Thus, the term failure rate is always referred as instantaneous failure rate not average failure rate. The fraction of devices that are good at time t and that fails by time t+t is given by F(t+t) F(t) = R(t) R(t+t) (1.57) The average failure rate during the time interval is given by Average failure rate = 1 R(t) R(t t) R(t) (1.58) In the limit as approaches zero, this becomes the instantaneous failure rate (t), which is given by 1 dr(t) ( t) R(t) dt (159) Integrating equation (1.55), it becomes t (x)dt ln[r(t)] (1.6) Thus, the reliability function R(t) is given by (t) exp t (x)dt R (1.61) A common measure of reliability is the mean time to failure (MTTF) of the device or system, which is defined as MTTF tf (t)dt (1.62) - 24 -

MTTF is the device s average age at failure for a population whose reliability function is R(t) with probability density function f(t). 1.4.3 Distribution Function of Failure Rate It is desired to have a distribution that represents the failure rate of device over its entire life. The failure of rate of an integrated circuit generally varies as a function of time following the manner shown in Fig1.1. Figure 1.1: Failure rate versus time for a typical integrated circuit During the early life of the device, the failure rate is high but it decreases as time passed. The failure during this period is called infant mortality failure. The causes of the early failure are generally fabrication and assembly related defects such as wire problem, micro-crack, over etch, photoresist residue, contamination, electrostatic defect etc. The defects can be wiped out by accelerated life test and followed by a final test to segregate them. The steady useful life period, the failure rate is normally low and the rate of failure is also fairly constant. Device failure in this period is a result of a large number of fabrication and assembly unrelated causes such as mishandling, applying wrong stimulant etc. The wear out period is the old age period, whereby the device has reached the end of its life. The simplest distribution for the failure rate is the exponential function, which is characterized by a constant failure rate over the entire life time of the device. This is the function of the steady useful life period, whereby all early infant mortality failure and wear out mechanism have been eliminated. Thus, - 25 -

the steady useful life failure rate function is (t) = = constant. From equation t (1.61), the reliability function R(t) is equal to R(t) e. The cumulative t distribution function is F(t) = 1 e, and probability density function is equal t to f(t) = e, and the mean time to failure (MTTF) is equal to t 1 te dt MTTF. Let s look at another failure rate function, which is the Weibull distribution function. The Weilbull states the failure rate varies as power of the age of the device. The failure rate is represented by 1 (t) t (1.63) where α and β are parameters of infant mortality failure distribution and is the steady useful-life failure rate. For β<1 the failure rate decreases with time, and Weibull distribution may be used to represent the early infant mortality failure. For β>1 the failure rate increases with time that can be used to represent the wear out period of the device. If β=1 then the failure rate is constant. The reliability function, fail function, probability distribution function, and mean time to failure are (t) t 1 exp t 1 R (t) exp t, 1 1/ f, and MTTF (1 1/ ) - 26 - respectively. 1 F (t) 1 exp t, In some applications of Weibull distribution function, a better fit to the experimental failure rate is by replacing the time t by (t-), represents that the portion of the life of the device has been used up during device manufacturing, device burn-in, or device testing. Log-normal distribution function is another common distribution used to describe the failure rate of the device. It has been quite successfully used to describe the failure rate of semiconductor device over long periods of time. Depending on the values of the parameters of the distribution, this function can represent any one of the three periods of the life of device as shown in Fig. 1.1. The probability distribution function of the log-normal distribution is given by 1 1 ln t (t) exp t 2 2 2 f (1.64)

1 1 exp ln t 2 2 t t 5 2 (1.65) where the median time to failure t 5, which is the time when 5% of the devices have failed is given by t 5 = e (1.66) The cumulative distribution function F(t) is given by 1 (t) t 2 t dx 1 ln t exp x 2 2 F (2.26) and the failure rate (t) is equal to f (t) (t) 1 F(t) (1.67) 1.4.4 Accelerated Testing In the previous section, we mentioned that a system operated in normal operating condition with 225 integrated circuits having failure rate 1 FIT requires 5.13 years to have first failure shown up. It is clearly impractical to study the failure characteristics of the device under the normal operating condition. Some means must be utilized to accelerate the mechanism that causes the unreliable device to fail earlier. The standards for accelerated tests of integrated circuit are mainly covered in various Test Methods of Mil-Std-883 specifications. For an example the burn-in test is covered by Method 115.9, while Method 11.8 is used for temperature cycle test. There are six common stress tests used to accelerate device failure. They are temperature, voltage, current, humidity, temperature cycling, and burn-in. Temperature cycle is used to accelerate mechanical failure of die and assembled package. This process is normally required for high reliable device such as the military graded device. The progress is done before gross and fine leak test in assembly process steps. - 27 -

1.4.4.1 Temperature Cycle The temperature cycle determines the ability of parts to resist extremely low and extremely high temperature, as well as its ability to withstand cyclical exposure to these temperature extreme. The devices are subjected to two extreme temperatures normally between -65 C and 175 C for minimum of 1 cycles. Each cycle takes approximately 21 minutes. The dwell time in each temperature is 1 minutes and the transfer time of the device between two temperature chambers is 1 minute. Another failure can be sorted out by fine/gross leakage test and test operation. 1.4.4.2 Temperature Acceleration Many of the mechanism are due to chemical or physical processes that can be accelerated by temperature. The reaction rate (R) at which these processes proceed is governed, in most of the time, by Arrhenius equation. R = R exp(-e a /kt) (1.68) where E a is the activation energy, k is the Boltzmann constant, and T is the temperature. As mention earlier, the increase of reaction rate with increase of temperature shall mean that the time to show a failure is shorter. Thus, the reaction rate R is inversely proportional to time t, which is also mean the Rt is a constant for a particular reaction type. Thus combining with equation (1.68), the ratio of the times to failure is given by t t 1 2 R R 2 1 E a exp k 1 T 1 1 T 2 (1.69) where temperature T 1 >T 2 and time t 1 < t 2. The ratio time to failure t 1 /t 2 is also termed as acceleration factor. 1.4.4.3 Voltage and Current Acceleration Voltage and current are effective accelerating stresses for many of the common failure mechanisms observed in integrated circuit. Voltage causes acceleration of failure caused by dielectric breakdown, interface charge accumulation, charge injection, and corrosion. - 28 -

Most studies indicate that the reaction rate of the failure mechanism is proportional to the power of the applied voltage. The power is usually a function temperature, which is R(T,V) R (1.7) (T) (T) V where (T) has a value between 1 to 4.5. In the case of dielectric breakdown, a different type of acceleration occurs. For given applied electric field a certain fraction of the devices fail in a very short time. Very few additional failures occur as the field is maintained. If the applied field is then increased further, an additional fraction of failures occur, again in a relatively short time. Device operation at increased current level is used primary to accelerate the failure due to electro-migration of metallic interconnect particular the aluminum interconnect. The reaction rate (R) of electro-migration is a function of temperature and current density (J), which follows equation (1.71). R(T,V) R (1.71) (T) (T) J where (T) has a value between 1 to 4.. It is usually not possible to independently vary the current in the device because the current in the device is determined by the circuit design. In normal case study like the electro-migration study, a special test structure is used. This structure is used to determine the maximum allowable current density for which the failure rate of conductor will be accepted. This maximum value is then used as the design guideline in the layout of the integrated circuit. 1.4.4.4 Humidity-Temperature Acceleration For a high reliability application integrated circuit device, it is usually packed in hermetic package that allowing evaluation and initial studies to be carried out under optimum conditions like the temperature cycle test for mechanical feature of the package, wire bonding strength, die and package material thermal coefficient expansion etc. Humidity-temperature acceleration test allows the acceleration of wafer vapor penetrating through the package especially the plastic package into the die with cracked passivation layer that would start the rapid electro-chemical - 29 -

corrosion process and subsequent showing up as device failure. Water vapor normally contains contaminant like sodium metallic ion and it can penetrate through crack and corrode the aluminum that would result in metal interconnect failure. For high reliable product, the leads of package especially the solder dipped and tin plated leads are subject to high humidity salt atmosphere condition for some time to check the corrosion level of the leads. 1.4.4.5 Burn-In Burn-in is a process used basically to wipe out infant mortality failure of the device so that the remaining devices can live from its steady useful life state to wear out end of life state. As already mentioned earlier, the causes of the early failure are generally fabrication and assembly related defects, through burn-in, time to failure due to these defects would usually show up in less than 168 hours. In integrated circuit assembly/test manufacturing, there are two schemes of burn-in done either in compliance with military or industrial specifications. The military devices are normally burn-in at temperature 15 C for 8 hours or temperature 125 C for 168 hours with both static and dynamic signals connected to the devices. Upon completion of burn-in, the devices are tested at temperature 25 C, 125 C, and -55 C to wipe failure due to fabrication and assembly processes. The industrial compliance devices are normally burn-in at temperature 85 C for 72 hours with static signals connected to the devices. Upon completion of burn-in, the devices are tested at temperature 25 C, 85 C, and -4 C to wipe failure due to fabrication process like contaminant and assembly process like crack, ESD failure. Normally these types of process faults are shown up as leakage test failure in final test. For the commercial compliance devices, no burn-in is done unless, it is a specially customer requirements. Exercises 1.1. What is the purpose of in-process quality control monitoring? 1.2. Name one rule to check if the SPC chart is normal. - 3 -

1.3. The data in the table are obtained from an operation in fabrication. Derive the values of SPC control lines for x i and R charts. Observation Observation x i Moving Range R 1 1.42-2 1.59.17 3 1.39.2 4 9.91.48 5 1.21.3 6 1.2.19 Mean x = 1.256 R =.268 1.4. Plot a SPC X chart and R chart of the control lines established in question 1.3. 1.5. The data in the table shown below are the current drain of eight integrated circuits measured by a piece of equipment in test operation. The specification limit of current drain is 1mA. Calculate the process capability index of this equipment and defective part per million produced by this equipment. Observation Observation x i 1 9. 2 9.2 3 9.9 4 9. 5 9.5 6 9.8 7 8.9 8 9.8 Mean x = 9.39 Standard Deviation s =.41 1.6. A particular system contains 2, transistors has failure rate 75 FIT, calculate the repair cost per month if each field engineer visit causes the company RM2,. - 31 -

1.7. Calculate the mean time between failures of the system that has data stated in question 1.6. 1.8. State how acceleration test method can be used to accelerate physical and chemical processes failure in shorten time. 1.9. State two acceleration stress tests that used to accelerate failure due to processes. 1.1. The V DD voltage for the voltage acceleration stress test for a device is set at 7.V instead of its normal operating voltage of 4.5V. If the time to fail at normal operation voltage is 15 years, calculate the time to fail for the device if voltage acceleration stress test is applied. You may use = 4 for your calculation. Answers of Exercises 1.1. The purpose is to ensure that the process of the device is done according to the specification. It is control point to ensure the quality of the product and minimizing the wastage due to producing defective device. 1.2. One of the rules is that there is a continuous seven consecutive points are either below the center line or above the center line. 1.3. The center line of the x i SPC is CL = 1.256, the lower control line LCL is x 2.66R = 9.543, while the upper control line UCL is x 2.66R = 1.256 2.66x.268= 1.959. The center line of the R SPC is CL =.268, the lower control line LCL is, while the upper control line UCL is 3.267R = 3.267x. 268=.876. 1.4. The X and R SPC charts are shown as follows: - 32 -

1.5. The process capability index is equal to C pk = - 33 - (USL ) 3 = ( 1 9.39) 3x.41.495. The probability of the defective part produced is P[z>3C pk ] = P[z > 1.49] = 1-.5-.4319 =.681, which is equal to 68,1 parts per million (pm). =

1.6. 75 FIT means the failure rate = 75x1-9 /Device-hr. Since the system has 2, transistors and the time of operation is 72hrs (one month). Thus, the number of transistor failure in a month is 75x1-9 x2,x72 = 1.8. Thus, the repair cost is approximately RM2, per month. 1.7. The mean time between failures can be calculated using equation 1Failure 1Failure Period of operation -9 No of transistor x 2, x 75x1 days. = 66.6 hrs = 2.8 1.8. High temperature acceleration test can used to accelerate failure due to physical and chemical processes. 1.9. Two of the many accelerated stress tests are temperature acceleration test and burn-in. 4 1.1. The rate of reaction at V DD equal to 4.5V is R(T,4.5V) R (T)4. 5 and the 4 reaction rate at V DD equals to 7.V is R(T,7.V) R (T)7.. The acceleration factor is R(T,7.V) R(T,4.5V) 4 R (T)7. 4 R (T)4.5 7. 4.5 4 = 5.855. If the time to fail at normal operation is 25 years, understand voltage acceleration stress, the time to fail will be 15 / 5. 855= 2.56 years. Bibliography 1. M Jeya Chandra, Statistical Quality Control, CRC Press LLC, 21. 2. S.M. Sze, VLSI Technology, New York, McGraw Hill, 22. 3. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic Digital Integrated Circuit A Design Perspective, 2 nd edition, Prentice Hall, 23. 4. C.Y. Chang and S.M. Sze, ULSI Technology, New York, McGraw Hill, 1996. - 34 -

Appendix A - 35 -

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