UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS 141 Spring 2003 Homework 10 Solutions Problem 1. Timing and Race Conditions a) First, we need to find the skew between the source register clock (φ ) and the destination register s clock (φ ). We can do this with a π2 model of the wire and the Elmore delay model. 150 Ω φ 200 Ω φ 600 ff 50 ff 50 ff 900 ff t φ = 0.69 (150) (650 f) = 67 ps t φ = 0.69 [ (150)(650 f) + (150+200)(950) ] = 297 ps δ = t φ - t φ = 230 ps (eq. 9.1) Next, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum. δ t r,min + t i + t l,min (eq. 9.2) t hold + δ t clk-q + t sum (modified to include hold time and to use the given quantities) 100 + 230 300 + 50 330 350 TRUE (barely)... Thus, this circuit has no race problem Lastly, we find the minimum clock period. Note that the maximum logic delay is a single sum plus the delay of the carry chain. T t r,max + t i + t l,max - δ (eq. 9.3) T t clk-q + 31 t carry + t sum - δ + t setup T 50 + (31)(250) + 300 230 + 150 T 8.02 ns (modified to include setup time and to use the given quantities) 1
b) Identical to part a), except the capacitance at φ is much less. 150 Ω φ 200 Ω φ 650 ff 350 ff t φ = 0.69 (150) (650 f) = 67 ps t φ = 0.69 [ (150)(650 f) + (150+200)(350) ] = 152 ps δ = t φ - t φ = 85 ps t hold + δ t clk-q + t sum 100 + 85 300 + 50 185 350 TRUE... Thus, no race problem Note, however, that this circuit has a much better margin of error than the one from part (a). T t clk-q + 31 t carry + t sum - δ + t setup T 50 + (31)(250) + 300 85 + 150 T 8.17 ns Note that the minimum cycle time is longer with the smaller skew. c) Identical to (a), except that the clock in driven in the other direction. φ 200 Ω φ 150 Ω 650 ff 950 ff t φ = 0.69 (150) (950 f) = 98 ps t φ = 0.69 [ (150)(950 f) + (150+200)(650) ] = 255 ps δ = t φ - t φ = -157 ps t hold + δ t clk-q + t sum 100-157 300 + 50-57 350 TRUE... Thus, no race problem Note that this circuit has the best margin of error over all three cases. 2
T t clk-q + 31 t carry + t sum - δ + t setup T 50 + (31)(250) + 300 + 157 + 150 T 8.41 ns Note that the minimum cycle time is the longest over all three cases. 3
Problem 3. Monostable Multivibrator Consider the monostable multivibrator circuit drawn below. Calculate the output pulse width. V t (dep) = -0.5V, V t = 0.4 V, K = 100µA/V 2, γ = 0 Assume Vin has been 0 for sometime and then suddenly switches to 2.4V. How wide is the pulse at the output (i.e. how long is V out high)? Assume that the output switches when the voltage on the gate input to the driver crosses 1.2 V. Initially the output is low, so the driver is on. Then when V in goes high, the driver turns of. Assume that the driver turns on again when its gate input voltage reaches 1.2V. When V in has been 0 for sometime, the 1nF capacitor is fully discharged. M4, M5, and M6 will always be on. When V in V dd, M1 turns on. Node X is driven towards GND. Due to large capacitance, node Y is pulled towards GND. This turns off M3. V out is pulled to V dd. M2 turns on. Node X is pulled even lower. M5 will charge up node Y. Time taken to charge node Y to V dd /2: I = C dv/dt I = I dsat (M5) = 0.5*k *2/16 * (0.8) 2 = 4A t = CV dd /2/I = 0.3ns As node Y crosses Vdd/2, M3 turns on, pulls Vout towards GND. M2 turns off, Voltage at X will jump slightly upwards. 1nF capacitance causes Node Y to jump slightly up. M3 strengthens it s pull of Vout to GND. M4 M5 M6 X Y M1 M2 M3 4
Problem 4. Timing Analysis a) Write down the necessary constraints on the clock skews to avoid race conditions. Let s try to build a table. This is not absolutely necessary, but may help identify critical sections: Source Destination Min Time Max Time Skew Constraints 1 RF PR 3 10 δ 2 δ 1 δ 2 δ 1 < 3 2 PR RF 2 8 - (δ 2 δ 1 ) δ 2 δ 1 > 2 3 PR IR 2 8 δ 3 δ 2 δ 3 δ 2 < 2 4 IR PR 4 15 -( δ 3 δ 2 ) δ 3 δ 2 > 4 5 IR RF 3 13 -( δ 3 δ 1 ) δ 3 δ 1 > 3 6 IR IR 3 13 0 2 < δ 2 δ 1 < 3 4 < δ 3 δ 2 < 2 δ 3 δ 1 > 3 b) Derive the constraints on the clock period in the presence of skew. Source Destination Min Time Max Time Skew Constraints 1 RF PR 3 10 δ 2 δ 1 Τ > 10 ( δ 2 δ 1 ) 2 PR RF 2 8 - (δ 2 δ 1 ) Τ > 8 + δ 2 δ 1 3 PR IR 2 8 δ 3 δ 2 Τ > 8 ( δ 3 δ 2 ) 4 IR PR 4 15 -( δ 3 δ 2 ) Τ > 15 + δ 3 δ 2 5 IR RF 3 13 -( δ 3 δ 1 ) Τ> 13 + δ 2 δ 1 6 IR IR 3 13 0 T > 13 c) Determine minimum possible clock period. Answer: 13 d) Determine the values of the skews for which this minimum period is achieved. δ 2 δ 1 = 0 δ 3 δ 2 = 2 If you had assumed δ 3 > δ 2 > δ 1 then u will want δ 3 δ 2 = 0; Τ>15 5
e) Propose a revised architecture that would reduce the clock period (changing circuit style is not an option). Explain your design, and discuss the disadvantages of your approach. RF DP1 DP2 E2 PR δ 1 δ 2 E1 FSM δ 3 IR Observe that whatever the skew, the critical path will always be for the signal to propagate from IR to either itself (13 ns), PR (15ns), or RF(13ns). By inserting an additional register E1 at the output of the FSM, we introduce a deeper pipeline and moved the critical path to DP1 (10ns). However, E1 is going to introduce delays and we should be careful how the FSM output is matched with the RF output. The easiest way is to note that the 2 feedback paths from DP2 output arrive at the inputs of DP1 at the same cycle: DP2 -> RF -> DP1 DP2 -> IR -> FSM -> DP1 In order to maintain the above order, E2 has to be added: DP2 -> RF -> E2 -> DP1 DP2 -> IR -> FSM -> E1 -> DP1 6