Lecture 10 OUTLINE. Reading: Chapter EE105 Spring 2008 Lecture 10, Slide 1 Prof. Wu, UC Berkeley

Similar documents
Lecture 36: MOSFET Common Drain (Source Follower) Amplifier.

ECEG 351 Electronics II Spring 2017

EE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers

ECEG 351 Electronics II Spring 2017

Lecture 25 ANNOUNCEMENTS. Reminder: Prof. Liu s office hour is cancelled on Tuesday 12/4 OUTLINE. General considerations Benefits of negative feedback

Lab 4: Frequency Response of CG and CD Amplifiers.

Lecture 21. REMINDERS Review session: Fri.11/9,3 5PMin306Soda in 306 (HP Auditorium) Midterm #2 (Thursday 11/15, 3:30 5PM in Sibley Auditorium)

EE 330 Lecture 30. Basic amplifier architectures

EE 330 Lecture 31. Basic amplifier architectures. Common Emitter/Source Common Collector/Drain Common Base/Gate

ECEN326: Electronic Circuits Fall 2017

EE5900 Spring Lecture 4 IC interconnect modeling methods Zhuo Feng

ECEN326: Electronic Circuits Fall 2017

Lecture 18. Common Source Stage

Mixed Signal IC Design Notes set 4: Broadband Design Techniques

Week 9: Multivibrators, MOSFET Amplifiers

Section J8b: FET Low Frequency Response

Chapter 11 Frequency Response. EE105 - Spring 2007 Microelectronic Devices and Circuits. High Frequency Roll-off of Amplifier. Gain Roll-off Thru C L

Analysis and Design of Analog Integrated Circuits Lecture 7. Differential Amplifiers

Introduction: the common and the differential mode components of two voltages. differential mode component: v d = v 1 - v 2 common mode component:

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER

A Novel PSR Enhancement Technique for Full on-chip Low-Dropout Regulator

EE 434 Lecture 16. Small signal model Small signal applications in amplifier analysis and design

Chapter 10 Objectives

Chapter 2 Resistive Circuits

EECE488: Analog CMOS Integrated Circuit Design. Set 2: Background

Reading. Lecture 28: Single Stage Frequency response. Lecture Outline. Context

HY:433 Σχεδίαση Αναλογικών/Μεικτών και Υψισυχνών Κυκλωμάτων

Lecture 28: Single Stage Frequency response. Context

Biasing the CE Amplifier

Chapter 2 Resistive Circuits

Transistor Characteristics and A simple BJT Current Mirror

EE105 Fall 2014 Microelectronic Devices and Circuits

EECE488: Analog CMOS Integrated Circuit Design. 3. Single-Stage Amplifiers

Introduction to CMOS RF Integrated Circuits Design

V. Transistors. 3.1 III. Bipolar-Junction (BJT) Transistors

Lecture 15: Differential Pairs (Part 2)

Vector Spaces in Physics 8/6/2015. Chapter 4. Practical Examples.

different formulas, depending on whether or not the vector is in two dimensions or three dimensions.

Lecture 4: RL Circuits. Inductive Kick. Diode Snubbers.

Final Exam Practice: Part II Math MULTIPLE CHOICE Choose the one alternative that best completes the statement or answers the question.

A nonstandard cubic equation

Chapter 5. BJT AC Analysis

Chapter 2. Small-Signal Model Parameter Extraction Method

ESE319 Introduction to Microelectronics Common Emitter BJT Amplifier

Active Circuits: Life gets interesting

EE 435 Lecture 13. Cascaded Amplifiers. -- Two-Stage Op Amp Design

1 S = G R R = G. Enzo Paterno

Exercises for Cascode Amplifiers. ECE 102, Fall 2012, F. Najmabadi

EE 321 Analog Electronics, Fall 2013 Homework #8 solution

EMA5001 Lecture 2 Interstitial Diffusion & Fick s 1 st Law. Prof. Zhe Cheng Mechanical & Materials Engineering Florida International University

Chapter 4: Techniques of Circuit Analysis

Lecture 28 Field-Effect Transistors

Chapter 28: Alternating Current

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

A Small-Signal Analysis of a BJT

The Operational Amplifier

Chapter 5 Solution P5.2-2, 3, 6 P5.3-3, 5, 8, 15 P5.4-3, 6, 8, 16 P5.5-2, 4, 6, 11 P5.6-2, 4, 9

Moment of Inertia. Terminology. Definitions Moment of inertia of a body with mass, m, about the x axis: Transfer Theorem - 1. ( )dm. = y 2 + z 2.

Feature Extraction Techniques

Active Circuits: Life gets interesting

Chapter 10: Sinusoidal Steady-State Analysis

Chapter 10 ACSS Power

th Annual IEEE Power Electronics Specialists Conference Aachen, Germany, Parallel Connection of Piezoelectric Transformers

Analysis of ground vibration transmission in high precision equipment by Frequency Based Substructuring

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C

High Speed Mixed Signal IC Design notes set 8. Noise in Electrical Circuits: circuit noise analysis

Section 1: Common Emitter CE Amplifier Design

Polytech Montpellier MEA M2 EEA Systèmes Microélectroniques. Analog IC Design

Active Circuits: Life gets interesting

(B) ' > 2 (A) ' < 2 (D) ' = 2 (C) > ' > 2. Page 1 of 6

Key Terms Electric Potential electrical potential energy per unit charge (JC -1 )

Lecture 17: Frequency Response of Amplifiers

Comparison of bulk driven, floating gate and sub threshold methods in designing of a typical amplifier

Unit 11: Vectors in the Plane

26 Impulse and Momentum

CHAPTER 13. Solutions for Exercises

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

HORIZONTAL MOTION WITH RESISTANCE

Design of CMOS Analog Integrated Circuits. Basic Building Block

Force and dynamics with a spring, analytic approach

ECEN326: Electronic Circuits Fall 2017

BJT Biasing Cont. & Small Signal Model

DESIGN OF MECHANICAL SYSTEMS HAVING MAXIMALLY FLAT RESPONSE AT LOW FREQUENCIES

Differential Amplifiers (Ch. 10)

A new small-signal RF MOSFET model

EE 435. Lecture 10: Current Mirror Op Amps

Energy and Momentum: The Ballistic Pendulum

EE C245 ME C218 Introduction to MEMS Design Fall 2011

8.012 Physics I: Classical Mechanics Fall 2008

figure shows a pnp transistor biased to operate in the active mode

Modeling Diaphragms in 2D Models with Linear and Nonlinear Elements

University of Pittsburgh

Polytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design

Chapter 10: Sinusoidal Steady-State Analysis

A Link Between Integrals and Higher-Order Integrals of SPN Ciphers

Definition of Work, The basics

Lectures 8 & 9: The Z-transform.

Relativity and Astrophysics Lecture 25 Terry Herter. Momenergy Momentum-energy 4-vector Magnitude & components Invariance Low velocity limit

before the collision and v 1 f and v 2 f after the collision. Since conservation of the linear momentum

Transcription:

Lecture 0 OUTLIN BJT Aplifiers (3) itter follower (Coon-collector aplifier) Analysis of eitter follower core Ipact of source resistance Ipact of arly effect itter follower with biasin eadin: Chapter 5.3.3-5.4 05 Sprin 2008 Lecture 0, Slide Prof. Wu, UC Berkeley

itter Follower (Coon Collector Aplifier) 05 Sprin 2008 Lecture 0, Slide 2 Prof. Wu, UC Berkeley

itter Follower Core When the input is increased by ΔV, output is also increased by an aount that is less than ΔV due to the increase in collector current and hence the increase in potential drop across. Howeer the absolute alues of input and output differ by a V B. 05 Sprin 2008 Lecture 0, Slide 3 Prof. Wu, UC Berkeley

Sall Sinal Model of itter Follower V A = out in = rπ β As shown aboe, the oltae ain is less than unity and positie. 05 Sprin 2008 Lecture 0, Slide 4 Prof. Wu, UC Berkeley

Unity Gain itter Follower V A A = = The oltae ain is unity because a constant collector current (= I ) results in a constant V B, and hence Vout follows Vin exactly. 05 Sprin 2008 Lecture 0, Slide 5 Prof. Wu, UC Berkeley

Analysis of itter Follower as a Voltae Diider V A = 05 Sprin 2008 Lecture 0, Slide 6 Prof. Wu, UC Berkeley

itter Follower with Source esistance V A = out in = S β 05 Sprin 2008 Lecture 0, Slide 7 Prof. Wu, UC Berkeley

Input Ipedance of itter Follower V i A X X = = r ( β ) π The input ipedance of eitter follower is exactly the sae as that of C stae with eitter deeneration. This is not surprisin because the input ipedance of C with eitter deeneration does not depend on the collector resistance. 05 Sprin 2008 Lecture 0, Slide 8 Prof. Wu, UC Berkeley

itter Follower as Buffer Since the eitter follower increases the load resistance to a uch hiher alue, it is suited as a buffer between a C stae and a heay load resistance to alleiate the proble of ain deradation. 05 Sprin 2008 Lecture 0, Slide 9 Prof. Wu, UC Berkeley

Output Ipedance of itter Follower s out = β itter follower lowers the source ipedance by a factor of β iproed driin capability. 05 Sprin 2008 Lecture 0, Slide 0 Prof. Wu, UC Berkeley

05 Sprin 2008 Lecture 0, Slide Prof. Wu, UC Berkeley itter Follower with arly ffect Since r O is in parallel with, its effect can be easily incorporated into oltae ain and input and output ipedance equations. ( )( ) O s out O S in S O O r r r r r A = = = β β β π

Current Gain There is a current ain of (β) fro base to eitter. ffectiely speakin, the load resistance is ultiplied by (β) as seen fro the base. 05 Sprin 2008 Lecture 0, Slide 2 Prof. Wu, UC Berkeley

itter Follower with Biasin A biasin technique siilar to that of C stae can be used for the eitter follower. Also, V b can be close to V cc because the collector is also at V cc. 05 Sprin 2008 Lecture 0, Slide 3 Prof. Wu, UC Berkeley

Supply Independent Biasin By puttin a constant current source at the eitter, the bias current, V B, and I B B are fixed reardless of the supply alue. 05 Sprin 2008 Lecture 0, Slide 4 Prof. Wu, UC Berkeley

Suary of Aplifier Topoloies The three aplifier topoloies studied so far hae different properties and are used on different occasions. C and CB hae oltae ain with anitude reater than one, while follower s oltae ain is at ost one. 05 Sprin 2008 Lecture 0, Slide 5 Prof. Wu, UC Berkeley

Aplifier xaple I out in = S β 2 The keys in solin this proble are reconizin the AC round between and 2, and Theenin transforation of the input network. 05 Sprin 2008 Lecture 0, Slide 6 Prof. Wu, UC Berkeley C S

Aplifier xaple II out C = S in β 2 Aain, AC round/short and Theenin transforation are needed to transfor the coplex circuit into a siple stae with eitter deeneration. 05 Sprin 2008 Lecture 0, Slide 7 Prof. Wu, UC Berkeley S

05 Sprin 2008 Lecture 0, Slide 8 Prof. Wu, UC Berkeley Aplifier xaple III The key for solin this proble is first identifyin eq, which is the ipedance seen at the eitter of Q 2 in parallel with the infinite output ipedance of an ideal current source. Second, use the equations for deenerated C stae with replaced by eq. 2 2 C in A r r = = β π π

Aplifier xaple IV A = S The key for solin this proble is reconizin that CB at frequency of interest shorts out 2 and proide a round for. appears in parallel with C and the circuit siplifies to a siple CB stae. 05 Sprin 2008 Lecture 0, Slide 9 Prof. Wu, UC Berkeley C

Aplifier xaple V in B = β β 2 The key for solin this proble is reconizin the equialent base resistance of Q is the parallel connection of and the ipedance seen at the eitter of Q 2. 05 Sprin 2008 Lecture 0, Slide 20 Prof. Wu, UC Berkeley

Aplifier xaple VI out 2 ro = S in 2 ro β S = r S out 2 O β The key in solin this proble is reconizin a DC supply is actually an AC round and usin Theenin transforation to siplify the circuit into an eitter follower. 05 Sprin 2008 Lecture 0, Slide 2 Prof. Wu, UC Berkeley

05 Sprin 2008 Lecture 0, Slide 22 Prof. Wu, UC Berkeley Aplifier xaple VII Ipedances seen at the eitter of Q and Q 2 can be luped with C and, respectiely, to for the equialent eitter and collector ipedances. ( ) 2 3 2 3 2 2 B B C B C out B in A r = = = β β β β β π