The K-Input Floating-Gate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate Oxide Bulk Cross-section p
Capacitive Voltage Dividers When trying to solve capacitor networks, it pays to think Q = CV rather than I= C dv dt C Q V Assume no net charge on the middle node. By conservation of charge, -Q 1 - Q 2 = 0 fi -C 1 ( -V )-C 2 ( -V)= 0 fi V = C 1 C 1 + C 2 + C 2 C 1 + C 2 Q 1 C 1 C 2 Q 2 V
Capacitive Voltage Dividers For all k, Q k = C k (V k - V ) Net charge Q on the common node. By conservation of charge, K -Â Q k =Q k=1 K ( ) fi -Â C k V k -V =Q k=1 K fivâ C k =Q + C k V k k=1 K Â k=1 C 1 Q 1 C 2 Q 2 V Q C K Q K V K fi V = Q C T + where C T K Â k =1 C k K Â k =1 C k C T V k
Capacitive-Divider Model of the Subthreshold FGMOS Transistor C gd C 1 C V FG 2 V D I C 1 C 2 C gd V D C C V ox dep FG ys V K C K Q C gs V S V K C K Q C gs V S C b C b V FG = Q C T + C gs C T V S + C gd C T V D + K Â C k C T V k I = I 0 e k QC T U T e k ( C 1 +L+C K V K ) C T U T e k C gd V D C T U T e k C gs V S C T U T ( e - V S U T - e - V D U T ) k=1 C T = ( C ox C dep )+C b +C gs +C gd + C k I = I 0 e k V FG U T ( e - V S U T - e - V D U T ) K Â k=1
Subthreshold FGMOS Transistor 10-6 10-7 10-8 Id (A) 10-9 10-10 10-11 n=4 n=3 n=2 n=1 10-12 0 0.5 1 1.5 2 2.5 3 (V) (4 n)c nc I d = I 0 exp n V C V C = 173 mv I 0 = 171 fa I d 5 V
10-6 Subthreshold FGMOS Transistor Id (A) 10-7 10-8 10-9 0.6 V 0.5 V 0.4 V 0.3 V 0.2 V 0.1 V =0 V 5 V 10-10 I d 10-11 10-12 0 0.5 1 1.5 2 2.5 3 (V) I d = I 0 exp + 3 V C V C = 173 mv I 0 = 171 fa
10-6 Subthreshold FGMOS Transistor: Drain Characteristics 0.7 V 10-7 0.6 V 10-8 0.5 V Id (A) 10-9 0.4 V 10-10 V g =0.3 V 10-11 10-12 I d = I 0 exp 4 V g V C I 0 = 171 fa exp V d 5 V V A V C = 173 mv 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V d (V) V g V A = 2.88 V I d V d
Subthreshold FGMOS Transistor: Drain Characteristics 3.5 3 I d (na) 2.5 2 1.5 1 V cas V g Cascoded FGMOS I d V d V g MOS V d I d FGMOS 2.93 V/e-fold V g 0.5 I d V d 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V d (V)
Capacitive-Divider Model of the Above-Threshold FGMOS Transistor C gd C 1 C V FG 2 V D I C 1 C 2 C gd V D C C V ox dep FG ys V K C K Q C gs V S V K C K Q C gs V S C b C b I = W L I = W L mc ox 2k mc ox 2k (( k( V FG - V T0 )-V S ) 2 -kv ( ( FG -V T0 )-V D ) 2 ) Ê Ê K Ê C k  k * Á Á Á V k -V T0 Ë Ë Ë k=1 C T ˆ ˆ -V S 2 Ê K Ê C - kâ k * Á Á V k -V T0 Ë Ë k=1c T ˆ -V D ˆ 2 ˆ V T0 * = V T0 - Q C T - C gs C T V S - C gd C T V D
Above-Threshold FGMOS Transistor 0.035 0.03 0.025 (4 n)c nc I 5 V I ( A) 0.02 0.015 I = na B A = 3.7 10 3 A/V B = 1.06 10 2 A n=4 n=3 0.01 0.005 n=2 0 0 0.5 1 1.5 2 2.5 3 (V) n=1
Above-Threshold FGMOS Transistor 8 10 3 7 I ( A) 6 5 4 3 2 1 I = A + 3A B A = 3.7 10 3 A/V B = 1.06 10 2 A I 5 V 0 0 0.5 1 1.5 2 2.5 3 (V) = 0.7 V 0.6 V 0.5 V 0.4 V 0.3 V 0.2 V 0.1 V
How to Make Leaky Floating Gates... Keep your floating gates on poly1. If you make a contact to metal, your gate will probably leak, because the oxide surrounding the metal layers are typically deposited rather than thermally grown.
Beware of Capacitive Coupling from Below... If possible, don't allow a floating gate to cross a well boundary. For a pfgmos, keep it entirely over the well. For an nfgmos, keep it entirely over the substrate. If you split the area evenly between the substrate and the well, your floating-gate voltage will have a dependence on V DD that you didn't expect...
Beware of Capacitive Coupling from Above... Be careful about routing metal lines over top of your floating gates. The voltages on such lines couple into the floating gate just like the control-gate voltages. Moreover, if you are trying to carefuly match C T for two FGMOS transistors, then you have to count the stray capacitance between these lines and the floating-gate too...
Which FGMOS Transistor Has a Higher Output Resistance?
Which FGMOS Transistor Has a Higher Output Resistance? The transistor on the left... For a FGMOS transistor, the Early effect (i.e., channel-length modulation) is always negligible compared to the effect of V D coupling through C gd to the floating gate. Increasing L does not increase r o. C gd µ W, so making the transistor wider decreases r o.
Matching: Same Size & Shape Reference Good Bad To obtain matched capacitive-divider ratios in different FGMOS transistors, use floating gates with identical geometries. Don't forget that C T includes parasitics that you won't be able to predict properly at design time.
Matching: Parallel Unit-Sized Control Gates Refernce Good Bad To obtain accurate control-gate capacitor ratios (e.g., 2:1), connect unit-sized control gates in parallel rather than making composite control gates with the correct area ratios. If you are trying to carefuly match C T, don t connect the unit-sized control gates on top of the floating gate.
dummy Matching: Same Surround dummy To improve control-gate matching, use dummy control gates at each end to make each real control gate have an identical surround. Systematic edge effects are ubiquitous, but the underlying mechanisms are not always clear (e.g., fringing fields, nonuniform etching rates).
Relative Capacitance vs Position 1.005 (1.2 mm Process) 1 Relative Capacitance 0.995 0.99 0.985 20 λ 20 λ 8 λ 8 λ 0.98 1 5 10 15 20 25 30 Position 32
Relative Capacitance vs Position 1.05 (.35 mm Process) 1.04 Relative Capacitance 1.03 1.02 1.01 20 λ 20 λ 8 λ 8 λ 1 0.99 1 5 10 15 20 25 30 32 Position
Experimental Method for Measuring Capacitor Matching b N 1 b 1 b 0 N-to-K decoder V g V c V k V K C 1 C 2 C k C K I fi In subthreshold, I µe k C i V i C T U T fi log I = kc i µ C i V i C T U T Mismatch in the slope of log I vs V i directly reflects mismatch in C i.