ENGG 1203 Tutorial. Solution (b) Solution (a) Simplification using K-map. Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives

Similar documents
ENGG 1203 Tutorial. Quick Checking. Solution. A FSM design for a Vending machine (Revisited) Vending Machine. Vending machine may get three inputs

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Lecture 10: Synchronous Sequential Circuits Design

EGR224 F 18 Assignment #4

Sequential Circuit Design

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Finite State Machines CS 64: Computer Organization and Design Logic Lecture #15 Fall 2018

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

Philadelphia University Student Name: Student Number:

Synchronous Sequential Circuit Design

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING COMPUTER SCIENCES DEPARTMENT UNIVERSITY OF WISCONSIN-MADISON

Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Fundamentals of Digital Design

Lecture 14 Finite state machines

Chapter 4. Sequential Logic Circuits

Example: vending machine

Lecture 7: Logic design. Combinational logic circuits

Combinational Logic. By : Ali Mustafa

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic

Finite State Machine (FSM)

Sequential Logic Circuits

Synchronous Sequential Circuit Design. Digital Computer Design

Philadelphia University Student Name: Student Number:

CPE100: Digital Logic Design I

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Chapter 7. Sequential Circuits Registers, Counters, RAM

Sample Test Paper - I

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

CMSC 313 Lecture 15 Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

University of Toronto Faculty of Applied Science and Engineering Final Examination

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

Different encodings generate different circuits

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Chapter 7 Logic Circuits

The Design Procedure. Output Equation Determination - Derive output equations from the state table

UNIVERSITI TENAGA NASIONAL. College of Information Technology

Digital Logic Appendix A

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

ENEL Digital Circuit Design. Final Examination

DIGITAL LOGIC CIRCUITS

Finite State Machine. By : Ali Mustafa

FSM model for sequential circuits

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

Module 10: Sequential Circuit Design

ELCT201: DIGITAL LOGIC DESIGN

MC9211 Computer Organization

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

Chapter 3 Combinational Logic Design

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

CMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

Digital Logic Design. Midterm #2

5 State Minimisation. university of applied sciences hamburg. Digital Systems. Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Lecture 8: Sequential Networks and Finite State Machines

Lecture 17: Designing Sequential Systems Using Flip Flops

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review.

Generalized FSM model: Moore and Mealy

CS61c: Representations of Combinational Logic Circuits

State Graphs FSMs. Page 1

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Models for representing sequential circuits

Example: A vending machine

EECS150 - Digital Design Lecture 23 - FSMs & Counters

CE1911 LECTURE FSM DESIGN PRACTICE DAY 1

T02 Tutorial Slides for Week 6

ECE 341. Lecture # 3

Systems I: Computer Organization and Architecture

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

Analysis of clocked sequential networks

CS/COE0447: Computer Organization

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

SAU1A FUNDAMENTALS OF DIGITAL COMPUTERS

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut

Appendix A: Digital Logic. CPSC 352- Computer Organization

Lecture 3 Review on Digital Logic (Part 2)

CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3

DE58/DC58 LOGIC DESIGN DEC 2014

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering


CPE100: Digital Logic Design I

Numbers and Arithmetic

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

Sequential Logic (3.1 and is a long difficult section you really should read!)

UC Berkeley College of Engineering, EECS Department CS61C: Representations of Combinational Logic Circuits

State and Finite State Machines

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

CSE140: Digital Logic Design Registers and Counters

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Propositional Logic. Logical Expressions. Logic Minimization. CNF and DNF. Algebraic Laws for Logical Expressions CSC 173

CS/COE0447: Computer Organization and Assembly Language

CPE100: Digital Logic Design I

UNIVERSITY OF WISCONSIN MADISON

Transcription:

ENGG 23 Tutorial Simplification using K-map Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives Apply Karnaugh map for logic simplification Design a finite state machine News HW (Feb 22, 23, :55pm) Ack.: HKU ELEC8, ISU CprE 28x, PSU CMPEN27, Wikipedia Simplify the Boolean expression of the circuit Change each NAND gate in the circuit to a NOR gate, and simplify the Boolean expression of the circuit M N Q x 2 (a) (b) M N Q x NQ M M N Q x NQ M From truth table to K-map x = MQ + NQ x = MN + Q 3 4

Finite State Machine (FSM) A simple Finite State Machine (FSM) State transition diagram Truth table K-Map Circuit State Present state: before the register Next state: after the register State transition: during clock 2 n states: n FFs Turnstile Control access Depositing a token in a slot on the turnstile unlocks the arms, allowing a single customer to push through. After the customer passes through, the arms are locked again until another coin is inserted. Current State Input Next State Output Locked Unlocked coin Unlocked Release turnstile so customer can push through push Locked None coin Unlocked None push Locked When customer has pushed through, lock turnstile 5 6 A simple FSM Steps in designing a state machine Current State Input Next State Output Locked Unlocked Specification FSM coin Unlocked Release turnstile so customer can push through push Locked None coin Unlocked None push Locked When customer has pushed through, lock turnstile State Arm: Arm: Transition Transition condition Draw a state transition diagram An initial state Other states to keep track of various activities Transitions Generate a state transition table and a output table Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions Draw the circuit 7 8

From state transition diagram to truth table Four states Two-bit state q: Present state q*: Next state z: Output From truth table to K-map A B D A D B D A D B Condition/Output 9 From K-map to circuit A simple FSM design State register Logic for state transition Logic for output Design a state machine that will repeatedly display in binary values (), 3 (), 5 (), and 7 () How many states we need? S, S, S2, S3 Simplified state transition diagram? 2

Output table L2 = XY'+XY = X L = X'Y+XY = Y L = X'Y'+X'Y+XY'+XY = State transition table X = X'Y+XY' Y = X'Y+XY' = Y' Current state Output S () () S () 3 () S2 () 5 () S3 () 7 () Current state Next state S () S () S () S2 () S2 () S3 () S3 () S () Current Output X Y L2 L L Current Next X Y X Y A complicated FSM design Vending Machine Collect money, deliver product and change Vending machine may get three inputs Inputs are nickel (5c), dime (c), and quarter (25c) Only one coin input at a time Product cost is 4c Does not accept more than 5c Returns 5c or c back Exact change appreciated 3 4 We are designing a Mealy state machine (i.e., output depends on both current state and inputs). Suppose we ask the machine to directly return the coin if it cannot accept an input coin. Input specification: I I 2 Represent the coin inserted - no coin ( cent), nickel (5 cents), dime ( cents), quarter (25 cents) Output specification: C C 2 P C C 2 represent the coin returned,,, P indicates whether to deliver product, States: S S 2 S 3 Represent the money inside the machine now 3 bits are enough to encode the states S ( cents) S5 (5 cents) S S5 S2 S25 S3 S35 5 6

Input Next state Output / / / / S35 / S35 / S / S / S35 S35: Currently the machine has 35 cents e.g. / : If we insert a quarter (), then the machine should return one quarter and zero product () 35c (35 cents inside the machine now) + 25c (insert 25 cents) = 35c (35 cents inside the machine in the next state) + 25c (return 25 cents) + c (return no product) 7 8 / / / / S35 / S35 / S / S / S35 e.g. /: If we insert a dime (), then the machine should return one nickel and one product () 35c (35 cents inside the machine now) + c (insert cents) = c (zero cent inside the machine in the next state) + 5c (return 5 cents) + 4c (return one product) e.g. /: If we insert a nickel (), then the machine should return zero coin and one product () 35c (35 cents inside the machine now) + 5c (insert 5 cents) = c (zero cent inside the machine in the next state) + c (return zero cent) + 4c (return one product) (Appendix) Simplification using K-map Simplify the following Boolean expressions using Karnaugh map. i) ( A + B)( A + B) ii) B + BC + ABC + AB 9 2

(Appendix) Counter i) ii) A/B A/BC ( A + B)( A + B) = A B + BC + ABC + AB = B + A Figure a) shows a complete four-bit parallel adder with registers and b) shows the signals used to add binary numbers from memory and store their sum in the accumulator. Suppose the numbers being added are and. Also assume that C o =. Describe what happen at t, t 2, t 3, t 4 and t 5. 2 22 At time t, is active low FF at the bottom will be cleared 23 24

At time t 2, load is active high Set A numbers will be loaded into the upper register At time t 3, transfer is active high Adder process between A 3 A 2 A A = and B 3 B 2 B B = At time t 4, the load is active high, the set B numbers will be loaded into register B on PGT of LOAD pulse B 3 B 2 B B = At time t 5, A 3 A 2 A A = and B 3 B 2 B B =, the adder produces S 3 S 2 S S =. This sum is transferred into register A when TRANSFER pulse occur at t 5. The sum S 3 S 2 S S = are transferred to register A on PGT due to this transfer pulse at t 3 25 26 (Appendix) State changing in FSM Design a 2-bit counter with input x that can be A down counter when x = ( ) A Johnson counter when x = ( ) 27 28

(Appendix) A typical FSM FSM Truth table Circuit State register Logic for state transition Logic for 29 output