74FR74 74FR1074 Dual D-Type Flip-Flop

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74FR74 74FR1074 Dual D-Type Flip-Flop General Description The 74FR74 and 74FR1074 are dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is traferred to the outputs on the rising edge of the clock input (CP n ). The 74FR1074 is the negative edge triggered version of this device. Both parts feature asynchronous clear (C Dn ) and set (S Dn ) inputs which are low level enabled. Ordering Code: Features Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. March 1992 Revised August 1999 74FR74 is pin-for-pin compatible with the 74F74 True 150 MHz f MAX capability on 74FR74 Outputs sink 24 ma and source 24 ma Guaranteed pin-to-pin skew specificatio Order Number Package Number Package Description 74FR74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74FR1074SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR1074PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74FR74 74FR1074 Dual D-Type Flip-Flop Connection Diagrams 74FR74 74FR1074 1999 Fairchild Semiconductor Corporation DS010977 www.fairchildsemi.com

74FR74 74FR1074 Logic Symbols 74FR74 Pin Descriptio Pin Names Description D n Data Inputs CP n Clock Inputs S Dn Asynchronous Set Inputs C Dn Asynchronous Clear Inputs Q n True Output Q n Complementary Output Truth Tables 74FR74 Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q 0 Q 0 74FR1074 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Rising Edge Q 0 = Previous Q(Q) before LOW-to-HIGH Clock Traition 74FR1074 Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q 0 Q 0 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial = Falling Edge Q 0 = Previous Q(Q) before HIGH-to-LOW Clock Traition www.fairchildsemi.com 2

Logic Diagrams 74FR74 74FR74 74FR1074 74FR1074 Please note that these diagrams are provided only for the understanding of logic operatio and should not be used to estimate propagation delays. 3 www.fairchildsemi.com

74FR74 74FR1074 Absolute Maximum Ratings(Note 1) Storage Temperature 65 C to +150 C Ambient Temperature under Bias 55 C to +125 C Junction Temperature under Bias 55 C to +150 C V CC Pin Potential to Ground Pin 0.5V to +7.0V Input Voltage (Note 2) 0.5V to +7.0V Input Current (Note 2) 30 ma to +5.0 ma Voltage Applied to Output in HIGH State (with V CC = 0V) Standard Output 0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (ma) ESD Last Passing Voltage (Min) 2000V Recommended Operating Conditio Free Air Ambient Temperature Supply Voltage 0 C to +70 C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditio is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter Min Typ Max Units V CC Conditio V IH Input HIGH Voltage 2.0 V Recognized HIGH Signal V IL Input LOW Voltage 0.8 V Recognized LOW Signal V CD Input Clamp Diode Voltage 1.2 V Min I IN = 18 ma V OH Output HIGH 2.5 V Min I OH = 1 ma Voltage 2.4 V Min I OH = 3 ma 2.0 V Min I OH = 24 ma V OL Output LOW Voltage 0.5 V Min I OL = 24 ma I IH Input HIGH Current 5 µa Max V IN = 2.7V I BVI Input HIGH Current Breakdown Test 7 µa Max V IN = 7.0V I IL Input LOW Current 150 µa Max V IN = 0.5V (D n, CP n ) 1.8 ma Max V IN = 0.5V (C Dn, S Dn ) V ID Input Leakage Test 4.75 V 0.0 I ID = 1.9 µa, All Other Pi Grounded I OD Output Circuit 3.75 V 0.0 V IOD = 150 mv, Leakage Test All Other Pi Grounded I OS Output Short-Circuit Current 100 275 ma Max V OUT = 0.0V I CEX Output HIGH 50 µa Max V OUT = V CC Leakage Current I CC Power Supply Current 24 ma Max www.fairchildsemi.com 4

AC Electrical Characteristics 74FR74 T A = +25 C T A = 0 C to +70 C Symbol Parameter Units Min Typ Max Min Max f MAX Maximum Clock Frequency 150 190 150 MHz t PLH Propagation Delay 2.5 3.5 5.0 2.5 5.0 t PHL CP n to Q n or Q n 2.5 4.5 6.0 2.5 6.0 t PLH Propagation Delay 1.5 3.5 5.5 1.5 5.5 t PHL C Dn or S Dn to Q n or Q n 2.0 5.5 7.0 2.0 7.0 74FR74 74FR1074 t OSHL t OSLH t OST t Q/Q t PS for HL Traitio for LH Traitio for HL/LH Traitio True/Complement Output Skew Pin (Signal) Traition Variation 1.0 1.0 3.0 1.8 1.8 Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specificatio apply to any outputs switching in the same direction either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ) or in opposite directio both HL and LH (t OST ). t OST is guaranteed by design. AC Operating Requirements 74FR74 T A = +25 C T A = 0 C to +70 C Symbol Parameter Units Min Max Min Max t S (H) Setup Time, HIGH or LOW 2.5 2.5 t S (L) D n to CP n 2.5 2.5 t H (H) Hold Time, HIGH or LOW 0 0 t H (L) D n to CP n 0 0 t W (H) CP n Pulse Width 3.3 3.3 t W (L) HIGH or LOW 3.3 3.3 (Note 4) t W (L) S Dn or C Dn Pulse Width 4.0 4.0 t REC Recovery Time 2.0 2.0 S Dn or C Dn to CP n Note 4: This specification is guaranteed by design. 5 www.fairchildsemi.com

74FR74 74FR1074 AC Electrical Characteristics 74FR1074 T A = +25 C T A = 0 C to +70 C Symbol Parameter Units Min Typ Max Min Max f MAX Maximum Clock Frequency 120 160 120 MHz t PLH Propagation Delay 2.5 4.0 5.5 2.5 5.5 t PHL CP n to Q n or Q n 3.0 5.0 6.5 3.0 6.5 t PLH Propagation Delay 1.5 3.5 5.5 1.5 5.5 t PHL C Dn or S Dn to Q n or Q n 2.0 5.5 7.0 2.0 7.0 t OSHL t OSLH t OST t Q/Q t PS for HL Traitio for LH Traitio for HL/LH Traitio True/Complement Output Skew Pin (Signal) Traition Variation 1.5 1.5 3.5 2.0 2.0 Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specificatio apply to any outputs switching in the same direction either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ) or in opposite directio both HL and LH (t OST ). t OST is guaranteed by design. AC Operating Requirements 74FR1074 T A = +25 C T A = 0 C = +70 C Symbol Parameter Units Min Max Min Max t S (H) Setup Time, HIGH or LOW 2.0 2.0 t S (L) D n to CP n 2.0 2.0 t H (H) Hold Time, HIGH or LOW 0 0 t H (L) D n to CP n 0 0 t W (H) CP n Pulse Width 3.3 3.3 t W (L) HIGH or LOW 3.3 3.3 (Note 6) t W (L) S Dn or C Dn Pulse Width 4.0 4.0 t REC Recovery Time S Dn or C Dn to CP n Note 6: This specification is guaranteed by design. 2.0 2.0 www.fairchildsemi.com 6

Physical Dimeio inches (millimeters) unless otherwise noted 74FR74 74FR1074 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 7 www.fairchildsemi.com

74FR74 74FR1074 Dual D-Type Flip-Flop Physical Dimeio inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any respoibility for use of any circuitry described, no circuit patent licees are implied and Fairchild reserves the right at any time without notice to change said circuitry and specificatio. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with itructio for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com