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INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC0 74C/CT/CU/CMOS ogic Family Specifications The IC0 74C/CT/CU/CMOS ogic Package Information The IC0 74C/CT/CU/CMOS ogic Package Outlines 74C/CT1 8-bit parallel-in/serial-out shift register File under Integrated Circuits, IC0 December 1990

74C/CT1 FEATURES Asynchronous 8-bit parallel load Synchronous serial input Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74C/CT1 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74C/CT1 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q 7 and Q 7 ) available from the last stage. When the parallel load (P) input is OW, parallel data from the D 0 to D 7 inputs are loaded into the register asynchronously. When P is IG, data enters the register serially at the D s input and shifts one place to the right (Q 0 Q 1 Q 2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q 7 output to the D S input of the succeeding stage. The clock input is a gated-or structure which allows one input to be used as an active OW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The OW-to-IG transition of input CE should only take place while CP IG for predictable operation. Either the CP or the CE should be IG before the OW-to-IG transition of P to prevent shifting the data when P is activated. APPICATIONS Parallel-to-serial data conversion QUICK REFERENCE DATA GND = 0 V; T amb = 2 C; t r = t f = ns SYMBO PARAMETER CONDITIONS C TYPICA CT UNIT t P / t P propagation delay CP to Q 7, Q 7 P to Q 7, Q 7 D 7 to Q 7, Q 7 C = 1 pf; V CC = V f max maximum clock frequency 48 Mz C I input capacitance 3. 3. pf C PD power dissipation capacitance per package notes 1 and 2 3 3 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1. V 1 1 11 11 ns ns ns ORDERING INFORMATION See 74C/CT/CU/CMOS ogic Package Information. December 1990 2

74C/CT1 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION 1 P asynchronous parallel load input (active OW) 7 Q 7 complementary output from the last stage 9 Q 7 serial output from the last stage 2 CP clock input (OW-to-IG edge-triggered) 8 GND ground (0 V) 10 D s serial data input 11, 12, 13,, 3, 4,, D 0 to D 7 parallel data inputs 1 CE clock enable input (active OW) 1 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. December 1990 3

74C/CT1 Fig.4 Functional diagram. FUNCTION TABE OPERATING MODES INPUTS Q n REGISTERS OUTPUTS P CE CP D S D 0 -D 7 Q 0 Q 1 -Q Q 7 Q 7 parallel load - - serial shift l h q 0 -q q q q 0 -q q q hold do nothing q 0 q 1 -q q 7 q 7 Note 1. = IG voltage level h = IG voltage level one prior to the OW-to-IG clock transition = OW voltage level I = OW voltage level one prior to the OW-to-IG clock transition q = lower case letters indicate the state of the referenced output one prior to the OW-to-IG clock transition = don t care = OW-to-IG clock transition Fig. ogic diagram. December 1990 4

74C/CT1 DC CARACTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CARACTERISTICS FOR C GND = 0 V; t r = t f = ns; C = 0 pf SYMBO t P / t P t P / t P t P / t P t T / t T t W t W t rem PARAMETER propagation delay 2 CE, CP to Q 7, Q 7 19 1 propagation delay P to Q 7, Q 7 0 18 propagation delay 3 D 7 to Q 7, Q 7 13 10 output transition time clock pulse width IG or OW parallel load pulse width; OW removal time P to CP, CE D s to CP, CE CE to CP; CP to CE D n to P T amb ( C) 74C +2 40 to +8 40 to +12 min. typ. max. min. max. min. max. 80 1 80 1 80 1 80 1 80 1 19 7 4 22 8 11 4 3 22 8 1 33 28 1 33 28 1 7 1 13 12 2 21 41 3 41 3 10 30 2 9 19 1 1 1 10 30 2 1 1 1 0 43 0 43 180 3 31 110 22 19 UNIT TEST CONDITIONS V CC (V) 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. WAVEFORMS December 1990

74C/CT1 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74C +2 40 to +8 40 to +12 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t h t h f max hold time D s to CP, CE D n to P hold time CE to CP CP to CE maximum clock pulse frequency 30 3 2 2 1 1 28 4 4. 4. Mz 2.0 4. December 1990

74C/CT1 DC CARACTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to CT types The value of additional quiescenpply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n D s CP CE P UNIT OAD COEFFICIENT 0.3 0.3 0. 0. 0. December 1990 7

74C/CT1 AC CARACTERISTICS FOR 74CT GND = 0 V; t r = t f = ns; C = 0 pf T amb ( C) TEST CONDITIONS 34 43 1 ns 4. 40 0 0 ns 4. 28 3 42 ns 4. 74CT SYMBO PARAMETER UNIT V WAVEFORMS +2 40 to +8 40 to +12 CC (V) min. typ. max. min. max. min. max. t P / t P propagation delay CE, CP to Q 7, Q 7 t P / t P propagation delay P to Q 7, Q 7 t P / t P propagation delay D 7 to Q 7, Q 7 t T / t T output transition time 7 1 19 22 ns 4. t W t W t rem t h t h f max clock pulse width IG or OW parallel load pulse width; OW removal time P to CP, CE D s to CP, CE CE to CP; CP to CE D n to P hold time D s to CP, CE; D n to P hold time CE to CP, CP to CE maximum clock pulse frequency 1 ns 4. 9 2 30 ns 4. 8 2 30 ns 4. 2 2 30 ns 4. 7 2 30 ns 4. 10 2 30 ns 4. 7 1 9 11 ns 4. 0 7 0 0 ns 4. 2 44 21 Mz 4. December 1990 8

74C/CT1 AC WAVEFORMS The changing to output assumes internal Q opposite state from Q 7. (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q 7 or Q 7 ) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. The changing to output assumes internal Q opposite state from Q 7. (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Waveforms showing the parallel load (P) pulse width, the parallel load to output (Q 7 or Q 7 ) propagation delays, the parallel load to clock (CP) and clock enable (CE) removal time. (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.8 Waveforms showing the data input (D n ) to output (Q 7 or Q 7 ) propagation delays when P is OW. December 1990 9

74C/CT1 CE may change only from IG-to-OW while CP is OW. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the set-up and hold times from the serial data input (D s ) to the clock (CP) and clock enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP) to the clock enable input (CE). (1) C : V M = 0%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times from the data inputs (D n ) to the parallel load input (P). PACKAGE OUTINES See 74C/CT/CU/CMOS ogic Package Outlines. December 1990 10