SILICON-ON-INSULATOR (SOI) technology has been

1122 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998 Monte Carlo Simulation of Electron Transport Properties in Extremely Thin SOI MOSFET s Francisco Gámiz, Member, IEEE, Juan A. López-Villanueva, Member, IEEE, Juan B. Roldán, Juan E. Carceller, Member, IEEE, and Pedro Cartujo, Member, IEEE Abstract Electron mobility in extremely thin-film siliconon-insulator (SOI) MOSFET s has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si SiO 2 interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film. Index Terms MOS devices, silicon-on-insulator technology. I. INTRODUCTION SILICON-ON-INSULATOR (SOI) technology has been suggested by several authors as an attractive future VLSI technology [1] [3] due to the advantages that SOI devices show when compared to their conventional silicon counterparts, in particular with respect to radiation tolerance, lower parasitic capacitance and short channel effects [2]. These advantages indicate a tremendous potential for extremely thin SOI devices and promise a very encouraging future for both SOI and VLSI technologies. It is important to note that we are not talking about new and completely unknown technology, but about an implementation [2] of very well-known classical SOI/SIMOX technology. After a long period of incubation, SOI technology now is in a period of rapid and successful development [4]. So much so that high-quality SOI transistors have already been built on Si layers as thin as 8 nm [5] [8]. In this work, the electron transport properties in ultrathin SOI MOSFET s are studied by simulation. In Section II of this paper, a quantum-mechanical calculation is implemented to evaluate the spatial and energy distribution of electrons in the SOI structure. To do so, the Poisson and Schrödinger equations have been self-consistently solved assuming a simple nonparabolic band model for the silicon. Once the actual potential distribution, inversion and depletion charge concentrations in the structure have been calculated, the electron dynamics are simulated by the one-electron Monte Carlo method in Section III. The behavior of electron mobility in such ultrathin Manuscript received May 27, 1997; revised October 22, 1997. The review of this paper was arranged by Editor S. Cristoloveanu. The authors are with the Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, 18071 Granada, Spain. Publisher Item Identifier S 0018-9383(98)02977-3. Fig. 1. Simulated SOI structure. silicon layers is analyzed in Section IV, including a careful study of the contribution of the different scattering mechanisms. Finally, in Section V, the main conclusions are drawn. II. SELF-CONSISTENT SOLUTION OF POISSON AND SCHRÖDINGER EQUATIONS The structure simulated consists of an undoped silicon film sandwiched by two oxide layers (Fig. 1). The gate-oxide thickness was taken as 5 nm, while the buried oxide was considered to be 80 nm thick. A P POLY gate was assumed. Different thicknesses of the silicon film ( ) ranging from 50 nm to 10 nm, were taken into account. The simulated devices are similar to those fabricated by other authors [7], [8]. In these structures, regardless of the potential well, the greatest extension of the carriers is limited by the silicon film thickness (due to the SiO barriers that surround the silicon film). In the devices considered here, the silicon film thicknesses, and therefore the maximum extension of the carriers, are comparable to their de Broglie wavelength. As a consequence, quantum size effects will be very important in the whole bias range, even at very low inversion charge concentrations. In this respect, Omura et al. [9] have shown that for silicon layer thicknesses of about 10 20 nm quantum effects become notable, and that, due to these size effects, an increase in the threshold voltage of the device can be observed as decreases. If we wish to accurately evaluate the distribution of the electrons in the structure for a given voltage applied between the gate and the substrate then we must solve Schrödinger s equation self-consistently with Poisson s equation. For the sake of simplicity, calculations are made in the Hartree approximation. Although this approximation may have serious drawbacks, the results obtained in its approach do not significantly change 0018 9383/98$10.00 1998 IEEE

GÁMIZ et al.: MONTE CARLO SIMULATION OF ELECTRON TRANSPORT PROPERTIES 1123 (a) (a) (b) (b) Fig. 2. Electron distribution and potential well for two different total charge concentrations: Dashed line: N inv =1210 12 cm 02. Solid line: N inv =8:8210 12 cm 02 ; (a) corresponds to a SOI structure with a silicon layer of Tw =10nm thick, while (b) corresponds to Tw =50nm. when the more complicated calculation procedure necessary to take into account many-body effects is used. (For a detailed discussion of this issue, see [10] [12]). To solve Poisson s equation we have considered a nonuniform adaptive mesh, employing an iterative-newton scheme. The actual band-bending through the whole structure and the finite height of the barrier at the Si SiO interfaces have been considered. A simple nonparabolic band model for the silicon has been taken into account. The procedure to obtain the solution of the Schrödinger equation for nonparabolic bands can be found elsewhere [13]. Fig. 2 shows the electron distribution in the structure and the potential well for two different silicon film thicknesses at room temperature. Fig. 2(a) corresponds to a structure with a silicon film thickness of 10 nm, while for Fig. 2(b) the silicon layer is 50 nm thick. In both cases, two gate biases have been considered: the dashed lines show a gate bias fixed to give a total electron concentration of cm, while the solid line indicates a gate bias fixed such that cm. In both cases, the silicon layer is very low doped and, therefore, completely depleted. It is interesting to note an important fact which can be observed by comparing Fig. 2(a) and (b). In Fig. 2(b), i.e., nm, carrier confinement near the interface is due to the potential well originated by the external bias, even at very low inversion-charge concentration. In contrast, in the case of the thinner silicon layer, Fig. 2(a), nm, carrier confinement is due to the proximity of the buried oxide to the gate oxide. In other words, the extension of the inversion layers is limited, in this second case, by the thickness of the silicon layer, instead of the potential well induced by the external bias Fig. 3. Electron distribution for two different Si layer thickness: dashed line: Tw =50nm, solid line: Tw =10nm; (a) corresponds to N inv =1210 12 cm 02, while (b) correspond to N inv =8:8210 12 cm 02. (as happens in thicker samples). As shown below, this behavior is fundamental to the understanding of the electron transport properties in a very thin SOI structure. To see this situation more clearly, Fig. 3 compares the spatial electron distribution for both silicon layer thicknesses, for the same inversioncharge concentration. It can be seen that for low inversioncharge concentrations, the carriers in the 10-nm device are more confined than in the 50-nm sample. In contrast, for high inversion-charge concentrations, the potential well induced by the external bias is thinner than the silicon layer, and therefore carriers are equally distributed in both cases. III. MONTE CARLO SIMULATION Once the actual potential distribution, inversion-and depletion-charge concentrations in the structure have been calculated, the effect of a constant electric field,, applied parallel to the interface is considered. This longitudinal electric field causes the inversion-layer electrons to drift in the direction parallel to the interface, undergoing different scattering mechanisms. The electron dynamics are simulated by the one-electron Monte Carlo method, described elsewhere [14] [16]. To do so, the trajectory of one-electron motion is followed for a long period, with the average drift velocity being calculated from the history of the electron motion for each longitudinal electric field value. The simulation begins with an electron in a given subband and with a wavevector. The longitudinal-electric field modifies the electron wavevector according to the semiclassical model during a free flight whose length is calculated as usual, taking into account the total scattering rate. The fast self-scattering procedure has been used. The semiclassical model has been

1124 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998 appropriately modified to include the nonparabolicity of the conduction band in the electron dynamics. The average drift velocity is calculated in this way for several values of the longitudinal electric field, and the low-electric field mobility is obtained from expression. In our Monte Carlo procedure we have allowed the electron to travel in six subbands and to move between them. The approach in which the above scattering mechanisms have been considered and the procedure to evaluate the scattering rates are identical to those used previously [14], [16], except for the inclusion of nonparabolicity. We have considered acoustic deformation potential scattering and intervalley phonon events. The phonon scattering rates for inversion layers have been deduced by using Price s formulation [17]. Surface-roughness scattering due to both interfaces has been considered in Ando s approach with an exponential model dependent on the spectral distribution of roughness at both interfaces. To take Coulomb scattering into account, we have developed a comprehensive model that simultaneously takes into consideration the effects of 1) screening by mobile carriers, 2) space correlation of the external charged centers (which may be important at high concentrations), 3) distribution of the charged centers in the oxide and semiconductor bulk, 4) electron distributions in the inversion layer, and 5) image effects caused by the difference in the dielectric constants of Si and SiO. The complete development of this Coulomb scattering model can be seen in [14] and [15]. In our procedure the electron energy has been limited to 0.5 ev, since for higher electron energies the results obtained by the simulation are not likely to be very accurate, as a detailed bandstructure was not used. In accordance with the above, as the silicon bandgap is set to 1.12 ev (and therefore this sets the energy threshold for the impact ionization process), impact ionization has not been included in our simulation. IV. ELECTRON MOBILITY Electron mobility is one of the most important factors to determine MOS device characteristics. Several groups have already experimentally studied this parameter in ultrathin SOI MOSFET s. A recent report stated that down to a silicon film thickness of 50 nm, the inversion-layer mobility of SOI MOSFET s is independent of the silicon film thickness [3]. However, a different behavior has been observed when Si film thickness falls below 20 nm [7], [8]. The results of these researchers show an abrupt mobility decrease in the device if the silicon film thickness is thinner than 20 nm. To study this behavior, we have calculated electron mobility in a single-gate SOI MOSFET for different silicon film thicknesses ( ) using the one-electron Monte Carlo simulator [14], [15] described in Section III. Fig. 4 shows electron mobility curves calculated at room temperature versus the transverse effective field. Effective electric field has been evaluated according to its definition by calculating the integral (1) Fig. 4. Electron mobility curves in a SOI MOSFET at room temperature for different silicon film thicknesses. Only surface-roughness (4 =2 Å, L =15 Å) and phonon scattering have been considered. The number in brackets indicates the thickness in nanometers of the silicon film. where is the inversion charge concentration and the local electric field. Only phonon and surface roughness scatterings have been taken into account in this figure. The number in brackets indicates the thickness (in nanometers) of the silicon film. For the surface-roughness scattering we considered an exponential model with the following parameters: Å, Å. We have assumed that both interfaces (back and gate interfaces) have the same surface roughness scattering parameters. Nevertheless, this could not be the case, and the back interface (interface between the silicon film and the buried oxide) could be rougher than the gate interface [2]. However, surface roughness scattering is important at high transverse effective fields, or high inversion layer concentrations. As shown above, at such inversion charge concentrations most of the electrons are confined near the gateoxide interface; therefore the role played by the back interface is much less important. As can be seen in this figure, the lower the Si film width, the lower the electron mobility at low inversion electron concentration, where phonon scattering is the main scattering mechanism (when Coulomb scattering is not present). Therefore, these results indicate that for the same inversion charge concentration, phonon scattering is greater for the thinnest silicon films. This behavior is due to the higher confinement of the inversion charge when the silicon film thickness decreases (see Section II), which produces a higher phononscattering rate, since more phonons can assist carrier transitions [12], [17] [19]. All in all, for the same inversion charge-concentration, the phonon scattering rate is greater in the thinnest films than in the thickest ones, and therefore a mobility reduction can be expected. Nevertheless, Fig. 4 shows that all the mobility curves tend to coincide at high inversion-charge concentrations. These can be explained as follows. 1) As shown in Fig. 3(b), carrier confinement at high charge concentrations tends to be similar, regardless of the silicon-layer thickness. Therefore, the same phonon scattering will be expected.

GÁMIZ et al.: MONTE CARLO SIMULATION OF ELECTRON TRANSPORT PROPERTIES 1125 are intrinsically linked to the very thin SOI devices. In any case, these explanations are complementary to that given in this paper, since all of them contribute to the mobility in the same way. Fig. 5. Electron mobility curves in a SOI MOSFET at room temperature for different silicon film thicknesses. Surface-roughness (4 =2Å, L =15Å) phonon and Coulomb scattering have been considered. An interface charge concentration of N it =0:5210 11 cm 02 has been assumed located in both interfaces. The number in brackets indicates the thickness in nanometers of the silicon film. 2) In addition, at high effective electric fields, the main scattering mechanism is surface-roughness scattering. We have also taken into account the effect of Coulomb scattering on the electron mobility curves. Fig. 5 shows electron mobility curves for the same samples considered in Fig. 4, but taking into consideration the effect of Coulomb scattering. We have assumed that an interface trap concentration of N cm exists in both interfaces. As can be observed, the same behavior occurs as in Fig. 4, i.e., the thinner the silicon film the lower the mobility. Therefore, the contribution of Coulomb scattering does not substantially modify the picture discussed above, when only phonon and surface-roughness scattering were considered. These results prove that the increase in the phonon scattering rate as a consequence of the greater confinement of carriers the thinner the silicon layer becomes, contributes to the decrease in the mobility found experimentally [7]. Other authors have provided different explanations for the mobility decrease as the silicon film thickness shrinks. Choi et al., for example, have claimed that the difference in the thermal expansion coefficients between silicon and oxide produces an increase in the lattice defects in the extremely thin silicon film sandwiched between the two oxides. This stress increase is held to be responsible for the mobility reduction in such extremely thin silicon films [7]. On the other hand, Toriumi et al. [8] attributed the mobility degradation to an increase in the Coulomb scattering rate in thinner SOI MOSFET s as a consequence of an increase in the interface trap density,, in the back interface. We have also studied the role played by a higher concentration of interface trap density in the back interface. As expected, a greater separation between mobility curves at low transverse effective fields is observed. This fact indicates that the greater degradation of the buried interface also contributes, as predicted in [8], to explaining the mobility decrease observed experimentally as decreases. Note that while the latter limitation is a consequence of technological problems, the other two reasons (phonon and stress limitations) V. CONCLUSIONS Extremely thin SOI devices have been studied by the Monte Carlo method. It has been shown that for the same inversion-charge concentration, the thinner the Si layer, the more confined the electrons are, and therefore the greater the phononscattering rate. A mobility decrease can thus be expected in the thinner devices and can in fact be seen in the simulated curves. We have thus shown that the mobility degradation experimentally observed when the Si layer thickness is under 20 nm thick receives the contribution of a greater phonon scattering rate. REFERENCES [1] M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, Two-dimensional simulation and measurement of high-performance MOSFET s made on a very thin SOI film, IEEE Trans. Electron Devices, vol. 36, pp. 493 503, Mar. 1989. [2] J.-P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI. Boston, MA: Kluwer, 1991. [3] J. Wang, N. Kistler, J. Woo, and C. R. Viswanathan, Mobility-field behavior of fully depleted SOI MOSFET s, IEEE Electron Device Lett., vol. 15, pp. 117 119, April 1994. [4] S. Cristoloveanu and S. S. Li, Electrical Characterization of Silicon on Insulator Materials and Devices. Norwood, MA: Kluwer, 1995. [5] Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, 0.1-m-gate, ultrathinfilm CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer in IEDM Tech. Dig., 1991, p. 675. [6] Y. Omura and K. Izumi, Quantum mechanical influences on shortchannel in ultra-thin MOSFET/SIMOX devices, IEEE Electron Devices Lett., vol. 17, pp. 300 302, June 1996. [7] J. H. Choi, Y. Park, and H. Min, Electron mobility behavior in extremely thin SOI MOSFET s, IEEE Electron Device Lett., vol. 18, pp. 527 529, Nov. 1995. [8] A. Toriumi, J. Koga, H. Satake, and A. Ohata, Performance and reliability concerns of ultra-thin SOI and ultra-thin gate oxide MOSFET s, in IEDM Tech. Dig., 1995, pp. 847 850. [9] Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, Quantum-mechanical effects on the threshold voltage of ultrathin-soi nmosfet s, IEEE Electron Device Lett., vol. 14, pp. 569 571, Oct. 1993. [10] T. Ouisse, Self-consistent quantum-mechanical calculations in ultrathin silicon-on-insulator structures, J. Appl. Phys., vol. 76, pp. 5979 5995, 1994. [11] T. Ando, A. B. Fowler, and F. Stern, Electronic properties of twodimensional systems, Rev. Mod. Phys., vol. 54, p. 437, 1982. [12] M. V. Fischetti and S. E. Laux, Monte Carlo study of electron transport in silicon inversion layers, Phys. Rev., vol. B48, p. 2244, 1993. [13] J. A. López-Villanueva, I. Melchor, P. Cartujo, and J. E. Carceller, Modified Schrödinger equation including nonparabolicity for the study of a two-dimensional electron gas, Phys. Rev., vol. B48, p. 1626, 1993. [14] F. Gámiz, J. A. López-Villanueva, J. A. Jiménez-Tejada, I. Melchor, and A. Palma, A comprehensive model for Coulomb scattering in inversion layers, J. Appl. Phys., vol. 75, p. 924, 1993. [15] F. Gámiz, J. A. López-Villanueva, J. Banqueri, J. Carceller, and P. Cartujo, Universality of electron mobility curves in MOSFET s: A Monte Carlo study, IEEE Trans. Electron Devices, vol. 42, p. 258, Feb. 1995. [16] F. Gámiz, I. Melchor, A. Palma, P. Cartujo, and J. A. López-Villanueva, Effects of oxide-charge space correlation on electron mobility in inversion layers, Semicond. Sci. Technol., vol. 9, pp. 1102 1107, 1994. [17] P. J. Price, Two-dimensional electron transport in semiconductor layers Part I: Phonon scattering, Ann. Phys. (USA), vol. 133, pp. 217 239, 1981. [18] K. Tomizawa, Numerical Simulation of Submicron Devices. Norwood, MA: Artech House, 1993, pp. 67 68. [19] B. K. Ridley, The electron phonon interaction in quasi-twodimensional semiconductor quantum wells structures, J. Appl. Phys. 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1126 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 5, MAY 1998 Francisco Gámiz (M 94) received the B.S. and M.Sc. degrees in physics in 1991, and the Ph.D. degree in 1994, both from the University of Granada, Granada, Spain. Currently, he is an Associate Professor at the University of Granada, where he has been working on the characterization of scattering mechanisms and their influence on the transport properties of charge carriers in semiconductor heterostructures since 1991. He has studied electron mobility in silicon inversion layers by Monte Carlo method. His current research interests include the effects of many-carriers on the electron mobility and the theoretical interpretation of the influence of high longitudinal electric fields have on the electric properties of MOS transistors. His current interests are also related to SiGe, SiC, SOI, and GaN devices, and quantum transport. He has coauthored several papers on all of the above subjects. Juan B. Roldán received the B.S. and M.Sc. degrees in physics in 1993 from the University of Granada, Granada, Spain. Currently, he is a Teaching Assistant at the University of Granada, where he has been working on the MOS device physics including 2-D transport, nonlocal effects, and Monte Carlo simulations since 1993. His current interests are also related to SiGe and SiC devices. Juan E. Carceller (M 83) received the B.S. and M.Sc. degrees in physics in 1975, and the Ph.D. degree in 1979, both from the University of Barcelona, Barcelona, Spain. Currently, he is a Professor at the University of Barcelona and the University of Granada, Granada, Spain. He was engaged in the research and characterization of deep levels in semiconductors. His current research interests include degradation of MOS structures and characterization of electron mobility in the channel of MOS transistors. Juan A. López-Villanueva (M 90) received the B.S. and M.Sc. degree in physics in 1984, and the Ph.D. degree in 1990, both from the University of Granada, Granada, Spain. His thesis was on the degradation of MOS structures by Fowler Nordheim tunneling. Currently, he is an Associate Professor at the University of Granada, where he has been working on deep-level characterization and, mainly, MOS device physics, including Fowler Nordheim and direct tunneling, quantum effects, 2 D transport, effects of nonparabolicity, scattering mechanisms, and Monte Carlo simulation of charge transport since 1985. He has coauthored several papers on all of the above subjects. His current research interests include the characterization, simulation, and modeling of electron devices, with emphasis on the MOS transistor. His educational activities also include analog systems for electronic instrumentation and power electronics. Pedro Cartujo (M 82) was born in La Bañeza, Leon, Spain, in 1936. He received the B.S. and M.Sc. degrees in physics in 1961, and the Ph.D. degree in 1969, both from the University of Madrid, Spain. His thesis was on automatic control. Currently, he is Head of the Department of Electronics and Computer Technology at the University of Granada, Granada, Spain. Prior to this position, he was a Researcher at the Superior Council for the Scientific Research, Spain, and Professor at the Universities of Valladolid, Barcelona, and Granada.