74HC1G125; 74HCT1G125

Similar documents
74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G02-Q100; 74HCT1G02-Q100

2-input EXCLUSIVE-OR gate

74HC1G125; 74HCT1G125

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74AHC1G00; 74AHCT1G00

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

Dual buffer/line driver; 3-state

NXP 74HC_HCT1G00 2-input NAND gate datasheet

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74AHC1G126; 74AHCT1G126

74HC2G08-Q100; 74HCT2G08-Q100

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

74AHC1G125; 74AHCT1G125

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

Dual buffer/line driver; 3-state

74AHC2G126; 74AHCT2G126

The 74LV08 provides a quad 2-input AND function.

74HC30-Q100; 74HCT30-Q100

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14.

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

Single supply translating buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

Bus buffer/line driver; 3-state

74AHC1G14; 74AHCT1G14

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2-input single supply translating NAND gate

74HC2G125; 74HCT2G125

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

The 74LV08 provides a quad 2-input AND function.

Octal buffer/line driver; 3-state

74AHC2G241; 74AHCT2G241

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

The 74LVC1G02 provides the single 2-input NOR function.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74HC365; 74HCT365. Hex buffer/line driver; 3-state

The 74AUP2G34 provides two low-power, low-voltage buffers.

The 74AXP1G04 is a single inverting buffer.

7-stage binary ripple counter

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

Low-power buffer with voltage-level translator

74HC2G14; 74HCT2G14. Dual inverting Schmitt trigger

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC03-Q100; 74HCT03-Q100

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC153-Q100; 74HCT153-Q100

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

Low-power configurable multiple function gate

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

Low-power configurable multiple function gate

74LV03. 1 General description. 2 Features and benefits. 3 Ordering information. Quad 2-input NAND gate

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74HC280; 74HCT bit odd/even parity generator/checker

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

Single dual-supply translating 2-input OR with strobe

The 74LVC1G11 provides a single 3-input AND gate.

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

Hex inverter with open-drain outputs

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74HC107-Q100; 74HCT107-Q100

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

Low-power 2-input NAND gate. The 74AUP1G00 provides the single 2-input NAND function.

The 74LV32 provides a quad 2-input OR function.

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

Dual supply buffer/line driver; 3-state

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC151-Q100; 74HCT151-Q100

Low-power dual Schmitt trigger inverter

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74LVC07A-Q100. Hex buffer with open-drain outputs

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74AVC General description. 2 Features and benefits. 1-to-4 fan-out buffer

Dual buffer/line driver; 3-state

Low-power 2-input AND gate with open-drain

The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption.

Octal bus transceiver; 3-state

74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate

74AUP1G04. 1 General description. 2 Features and benefits. Low-power inverter

Octal bus transceiver; 3-state

Low-power triple buffer with open-drain output

Transcription:

Rev. 6 6 September 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV 4 Marking Table 2. Marking The is a single buffer/line driver with 3-state output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to s in excess of V CC. Wide supply range from 2.0 V to 6.0 V Input levels: For 74HC1G125: CMOS level For 74HCT1G125: TTL level Low power dissipation Symmetrical output impedance High noise immunity Balanced propagation delays ESD protection HBM EI/JESD22-114-C exceeds 2000V MM EI/JESD22-115- exceeds 200V Specified from 40 C to 85 C and 40 C to 125 C Package Temperature range Name Description Version -40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 -40 C to +125 C SC-74 plastic surface mounted package; 5 leads SOT753 Type number Marking code [1] 74HC1G125GW 74HCT1G125GW HM TM

Type number Marking code [1] 74HC1G125GV 74HCT1G125GV H25 T25 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram 2 1 OE Y mna118 4 2 1 EN mna119 4 OE mna120 Y Figure 1. Logic symbol Figure 2. IEC logic symbol Figure 3. Logic diagram 6 Pinning information 6.1 Pinning 74HC1G125GW 74HCT1G125GW 74HC1G125GV 74HCT1G125GV OE 1 5 V CC OE 1 5 V CC 2 2 GND 3 4 Y GND 3 4 Y 001aad948 Figure 4. Pin configuration TSSOP5 001aad949 Figure 5. Pin configuration SC-74 6.2 Pin description Table 3. Pin description Symbol Pin Description OE 1 output enable input (active LOW) 2 data input GND 3 ground (0 V) Y 4 data output V CC 5 supply 2 / 14

7 Functional description Table 4. Function table [1] Control Input Output OE Y L L L L H H H X Z [1] H = HIGH level; L = LOW level; X = don t care; Z = high-impedance OFF-state. 8 Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply -0.5 +7.0 V I IK input clamping current V I < -0.5 V or V I > V CC + 0.5 V I OK output clamping current V O < -0.5 V or V O > V CC + 0.5 V I O output current V O = -0.5 V to (V CC + 0.5 V) [1] [1] [1] - ±20 m - ±20 m - ±35 m I CC supply current - 70 m I GND ground current -70 - m T stg storage temperature -65 +150 C P tot total power dissipation T amb = -40 C to +125 C [2] - 200 mw [1] The input and output ratings may be exceeded if the input and output current ratings are observed. [2] bove 55 C the value of P tot derates linearly with 2.5 mw/k. 9 Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC1G125 74HCT1G125 Unit Min Typ Max Min Typ Max V CC supply 2.0 5.0 6.0 4.5 5.0 5.5 V V I input 0 - V CC 0 - V CC V V O output 0 - V CC 0 - V CC V T amb ambient temperature -40 +25 +125-40 +25 +125 C Δt/ΔV input transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/v V CC = 4.5 V - 1.67 139-1.67 139 ns/v V CC = 6.0 V - - 83 - - - ns/v 3 / 14

10 Static characteristics Table 7. Static characteristics 74HC1G125 t recommended operating conditions; s are referenced to GND (ground = 0 V). Symbol Parameter Conditions T amb = 40 C to +85 C T amb = 40 C to +125 C Unit Min Typ [1] Max Min Max V IH V IL V OH V OL HIGH-level input LOW-level input HIGH-level output LOW-level output V CC = 2.0 V 1.5 1.2-1.5 - V V CC = 4.5 V 3.15 2.4-3.15 - V V CC = 6.0 V 4.2 3.2-4.2 - V V CC = 2.0 V - 0.8 0.5-0.5 V V CC = 4.5 V - 2.1 1.35-1.35 V V CC = 6.0 V - 2.8 1.8-1.8 V V I = V IH or V IL I O = -20 μ; V CC = 2.0 V 1.9 2.0-1.9 - V I O = -20 μ; V CC = 4.5 V 4.4 4.5-4.4 - V I O = -20 μ; V CC = 6.0 V 5.9 6.0-5.9 - V I O = -6.0 m; V CC = 4.5 V 3.84 4.32-3.7 - V I O = -7.8 m; V CC = 6.0 V 5.34 5.81-5.2 - V V I = V IH or V IL I O = 20 μ; V CC = 2.0 V - 0 0.1-0.1 V I O = 20 μ; V CC = 4.5 V - 0 0.1-0.1 V I O = 20 μ; V CC = 6.0 V - 0 0.1-0.1 V I O = 6.0 m; V CC = 4.5 V - 0.15 0.33-0.4 V I O = 7.8 m; V CC = 6.0 V - 0.16 0.33-0.4 V I I input leakage current V I = V CC or GND; V CC = 6.0 V - - 1.0-1.0 μ I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; V CC = 6.0 V I CC supply current V I = V CC or GND; I O = 0 ; V CC = 6.0 V - - 5-10 μ - - 10-20 μ C I input capacitance - 1.5 - - - pf [1] ll typical values are measured at T amb = 25 C. 4 / 14

Table 8. Static characteristics 74HCT1G125 t recommended operating conditions; s are referenced to GND (ground = 0 V). Symbol Parameter Conditions T amb = 40 C to +85 C T amb = 40 C to +125 C Unit Min Typ [1] Max Min Max V IH V IL V OH V OL HIGH-level input LOW-level input HIGH-level output LOW-level output V CC = 4.5 V to 5.5 V 2.0 1.6-2.0 - V V CC = 4.5 V to 5.5 V - 1.2 0.8-0.8 V V I = V IH or V IL ; V CC = 4.5 V I O = -20 μ 4.4 4.5-4.4 - V I O = -6.0 m 3.84 4.32-3.7 - V V I = V IH or V IL ; V CC = 4.5 V I O = 20 μ - 0 0.1-0.1 V I O = 6.0 m - 0.16 0.33-0.4 V I I input leakage current V I = V CC or GND; V CC = 5.5 V - - 1.0-1.0 μ I OZ OFF-state output current V I = V IH or V IL ; V O = V CC or GND; V CC = 5.5 V I CC supply current V I = V CC or GND; I O = 0 ; V CC = 5.5 V ΔI CC additional supply current V I = V CC - 2.1 V; I O = 0 ; V CC = 4.5 V to 5.5 V - - 5-10 μ - - 10-20 μ - - 500-850 μ C I input capacitance - 1.5 - - - pf [1] ll typical values are measured at T amb = 25 C. 5 / 14

11 Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 8 Symbol Parameter Conditions T amb = -40 C to +125 C Unit Min Typ [1] Max +85 C Max +125 C 74HC1G125 t pd t en t dis C PD 74HCT1G125 t pd propagation delay enable time disable time power dissipation capacitance propagation delay to Y; see Figure 6 [2] V CC = 2.0 V - 24 125 150 ns V CC = 4.5 V - 10 25 30 ns V CC = 5 V; C L = 15 pf - 9 - - ns V CC = 6.0 V - 8 21 26 ns OE to Y; see Figure 7 [2] V CC = 2.0 V - 19 155 190 ns V CC = 4.5 V - 9 31 38 ns V CC = 6.0 V - 7 26 32 ns OE to Y; see Figure 7 [2] V CC = 2.0 V - 18 155 190 ns V CC = 4.5 V - 12 31 38 ns V CC = 6.0 V - 11 26 32 ns V I = GND to V CC [3] to Y; see Figure 6 t en enable time V CC = 4.5 V; OE to Y; see Figure 7 t dis disable time V CC = 4.5 V; OE to Y; see Figure 7 C PD power dissipation capacitance [2] - 30 - - pf V CC = 4.5 V - 11 30 36 ns V CC = 5 V; C L = 15 pf - 10 - - ns V I = GND to V CC - 1.5 V [2] [2] [3] - 10 35 42 ns - 11 31 38 ns - 27 - - pf [1] ll typical values are measured at T amb = 25 C. [2] t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. [3] C PD is used to determine the dynamic power dissipation (P D in μw). P D = C PD V CC 2 fi N + Σ(C L V CC 2 fo ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply in V; N = number of inputs switching; Σ(C L V CC 2 fo ) = sum of the outputs. 6 / 14

11.1 Waveforms and test circuit V I input GND t PHL t PLH Y output Measurement points are given in Table 10. Figure 6. Propagation delay data input () to output (Y) 001aad070 V I OE input GND output LOW-to-OFF OFF-to-LOW V CC V OL t PLZ t PHZ V X t PZL t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND Measurement points are given in Table 10. outputs enabled V Y outputs disabled V OL and V OH are typical output levels that occur with the output load. Figure 7. Enable and disable times outputs enabled mna644 Table 10. Measurement points Type Input Output V X V Y 74HC1G125 0.5V CC 0.5V CC V OL + 0.3 V V OH - 0.3 V 74HCT1G125 1.3 V 1.3 V V OL + 0.3 V V OH - 0.3 V 7 / 14

t W V I negative pulse 0 V 90 % 10 % t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC G VI DUT VO RL S1 open RT CL 001aad983 Test data is given in Table 11. Definitions for test circuit: R T = Termination resistance should be equal to the output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistance S1 = Test selection switch Figure 8. Test circuit for measuring switching times Table 11. Test data Type Input Load S1 position V I t r, t f C L R L t PLH, t PHL t PZH, t PHZ t PZL, t PLZ 74HC1G125 V CC 6 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT1G125 3 V 6 ns 15 pf, 50 pf 1 kω open GND V CC 8 / 14

12 Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E X c y H E v M Z 5 4 2 1 ( 3 ) θ 1 3 e b p e 1 w M detail X L p L 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1.1 0.1 0 2 3 b p c D (1) E (1) e e 1 H E L L p v w y Z (1) θ 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT353-1 MO-203 SC-88 EUROPEN PROJECTION ISSUE DTE 00-09-01 03-02-19 Figure 9. Package outline SOT353-1 (TSSOP5) 9 / 14

Plastic surface-mounted package; 5 leads SOT753 D B E X y H E v M 5 4 Q 1 c 1 2 3 Lp e b p w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 bp c D E e H E L p Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT753 SC-74 02-04-16 06-03-16 Figure 10. Package outline SOT753 (SC-74) 10 / 14

13 bbreviations Table 12. bbreviations cronym CMOS DUT ESD HBM MM TTL Description Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14 Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT1G125 v.6 20170906 Product data sheet - 74HC_HCT1G125 v.5 Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74HC_HCT1G125 v.5 20051223 Product data sheet ECN05_085 74HC_HCT1G125 v.4 Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. In Table 5 Limiting values I O : changed max value ±12.5 into ±35 I CC : changed max value 25 into 70 I GND : changed max value -25 into -70 In Table 7 Static characteristics 74HC1G125 V OH : changed condition I O = -2.0 m into I O = -6.0 m and min value from 4.13 into 3.84 V OH : changed condition I O = -2.6 m into I O = -7.8 m and min value from 5.63 into 5.34 V OL : changed condition I O = 2.0 m into I O = 6.0 m V OL : changed condition I O = 2.6 m into I O = 7.8 m V OH : changed condition I O = -2.0 m into I O = -6.0 m V OL : changed condition I O = 2.0 m into I O = 6.0 m In Table 8 Static characteristics 74HCT1G125 V OH : changed condition I O = -2.0 m into I O = -6.0 m and min value from 4.13 into 3.84 V OL : changed condition I O = 2.0 m into I O = 6.0 m and typ value from 0.15 into 0.16 V OH : changed condition I O = -2.0 m into I O = -6.0 m V OL : changed condition I O = 2.0 m into I O = 6.0 m 74HC_HCT1G125 v.4 20040727 Product specification - 74HC_HCT1G125 v.3 74HC_HCT1G125 v.3 20020517 Product specification - 74HC_HCT1G125 v.2 74HC_HCT1G125 v.2 20010302 Product specification - 74HC_HCT1G125 v.1 74HC_HCT1G125 v.1 19981110 Product specification - - 11 / 14

15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia's aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 12 / 14

Non-automotive qualified products Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 13 / 14

Contents 1 General description... 1 2 Features and benefits...1 3 Ordering information... 1 4 Marking...1 5 Functional diagram...2 6 Pinning information... 2 6.1 Pinning...2 6.2 Pin description... 2 7 Functional description...3 8 Limiting values...3 9 Recommended operating conditions... 3 10 Static characteristics...4 11 Dynamic characteristics...6 11.1 Waveforms and test circuit... 7 12 Package outline...9 13 bbreviations... 11 14 Revision history... 11 15 Legal information...12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. Nexperia B.V. 2017. ll rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 6 September 2017 Document identifier: 74HC_HCT1G125