Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the gate. Symbols NMOS PMOS NMOS (n-type MOS transistor (1 Majority carrier = electrons ( A positive voltage applied on the gate with respect to the substrate enhances the number of electrons the channel and hence creases the conductivity of the channel. (3 If gate voltage is less than a threshold voltage t, the channel is cut-off (very low current between source & dra. PMOS (p-type MOS transistor (1 Majority carrier = holes 1
( Applied voltage is negative with respect to substrate. Threshold voltage (t: The voltage at which an MOS device begs to conduct ("turn on" Relationship between gs (gate-to-source voltage and the source-to-dra current (Ids, given a fixed dra-to-source voltage (ds. (1 Devices that are normally cut-off with zero gate bias are classified as "enhancement-mode "devices. ( Devices that conduct with zero gate bias are called "depletion-mode "devices. (3 Enhancement-mode devices are more popular practical use.
.1.1 NMOS Enhancement Transistor Consist of (1 Moderately doped p-type silicon substrate ( Two heavily doped n + regions, the source and dra, are diffused. (3 Channel is covered by a th sulatg layer of silicon dioxide (SiO called " Gate Oxide " (4 Over the oxide is a polycrystalle silicon (polysilicon electrode, referred to as the "Gate" Features (1 Sce the oxide layer is an sulator, the DC current from the gate to channel is essentially zero. ( No physical distction between the dra and source regions. (3 Sce SiO has low loss and high dielectric strength, the application of high gate fields is feasible. In operation (1 Set ds > 0 operation ( gs =0 no current flow between source and dra. They are 3
sulated by two reversed-biased PN junctions (see Fig.3. (3 When g > 0, the produced E field attracts electrons toward the gate and repels holes. (4 If g is sufficiently large, the region under the gate changes from p-type to n-type(due to accumulation of attracted elections and provides a conductg path between source and dra. The th layer of p-type silicon is said to be "verted". (5 Three modes (see Fig.4 a. Accumulation mode (gs << t b. Depletion mode (gs =t c. Inversion mode (gs > t 4
Electrically (1 An MOS device can be considered as a voltage-controlled switch that conducts when gs >t (given ds>0 ( An MOS device can be considered as a voltage-controlled resistor (See Fig.5 Effective gate voltage (gs-t At the source end, the full gate voltage is effective the vertg the channel. At the dra end, only the difference between the gate and dra voltage is effective 5
Pch-off (1 ds > gs-t => gd < t => d > g t (g is not big enough ( The channel no longer reaches the dra. (Fig.5 c (3 As electrons leave the dra depletion region and are subsequently accelerated toward the dra. (4 The voltage across the pched-off region remas at (gs-t => saturated state which the channel current as controlled by g, and is dependent of d For fixed ds and g, Ids is function of (1 Distance between dra & source ( Channel width (3 t (4 Thickness of gate oxide (5 The dielectric constant of gate oxide (6 Carrier (hole or electron mobility, μ. Conductg mode (1 cut-off region : Ids 0, gs < t ( Nonsaturated region : weak version region, when Ids depends on g & d (3 Saturated region: channel is strongly verted and Ids is ideally dependent of ds (pch-off region (4 Avalanche breakdown (pch-through : very high d => gate has no control over Ids 6
.1. PMOS Enhancement Transistor (1 g < 0 ( Holes are major carrier (3 d < 0, which sweeps holes from the source through the channel to the dra..1.3 Threshold voltage A function of (1 Gate conductor material ( Gate sulator material (3 Gate sulator thickness (4 Impurity at the silicon-sulator terface (5 oltage between the source and the substrate sb (6 Temperature a. -4 m/ C high substrate dopg b. - m/ C low substrate dopg 7
. MOS equations..1 Basic DC equations Three MOS operatg regions (1 Cutoff or subthreshold region I ds =0, gs t ( Nonsaturation, lear or triode region ( ds gs t ds I ds = 0<gs<gs-t [ gs t ] ds When ds << gs-t (3 Saturation region I ( gs t ds =, 0< gs-t<ds d at which the device becomes saturated is called dsat (dra saturation voltage 8
: MOS transistor ga factor Function of (1 process parameter ( device geometry (1 μ= effective mobility of the carrier the channel ( ε= permittivity of the gate oxide (3 t ox = thickness of the gate oxide ε W Note: = Cox => = µc ox t L ox Example Typical CMOS (~1μ process (1 μ n =500 cm /-sec ( ε=3.9ε 0 =3.9*8.85*10-14 F/cm (permittivity of SiO (3 t ox =00 Α µε W W n = = 88.5 µ Α / L L t ox cm sec W L µ Α µ p = 180 => p = 31.9 N =. 8 p (~3 dependg on process 9
... Seven Second-order Effect SPICE : Simulation Program with Integrated Circuit Emphasis LEEL: 1,,3 (1 Basic DC Equations + Some second-order effects ( Based on device physics (3 Add more parameters to match real circuits e.g., Process ga factor SPICE : Kp (10-100 μa/ with 10%-0% variation A. Channel-length modulation When an MOS device is saturation. L eff = L - L short L short = ε si qn A ( ds ( gs t =>L => => Ids I ds With ( ( + λ K W = gs t 1 L K = µε : process ga factor t ox ds λ:channel length modulation factor (0.0-1 to 0.005-1 (In SPICE level 1 : λ=lambda B. Dra punchthrough (avalanche breakdown D is very high, Ids is dependent of gs Good for I/O protection circuit. 10
C. Threshold voltage (t Body effect (sb t = fb + φ + b ε si qn A ( φ + C => t = t 0 + γ [ φ b + SB φ b ] (1 sb : substrate bias ( t0 : t at sb=0 ox b (3 γ:a constant which describes the substrate bias effect (range:0.4~1. (4 SPICE t SB ox γ = qε sin A = ε ox Cox γ: GAMMA SPICE model to : T0 N A : NSUB ψ s = ψ b : PHI (the surface potential at the onset of strong version Subthreshold region Cut-off = subthreshold region Ids 0 (Subthreshold region But the fite value of Ids may be used to construct very low power circuits. In Level 1 SPICE, subthreshold current is set 0 1 qε Others: - Mobility variation - Fowler-Nordheim Tunnelg - Impact Ionization (Hot electrons effect si N A 11
..3 MOS Models MOS model = ideal equation + second-order + additional parameters Many semiconductor vendors expend a lot of effects to model the devices they manufacture.(standard : Level 3 SPICE Ma SPICE DC parameters level 1,,3 1μn-well CMOS process. 1
.3 CMOS verter DC characteristics turn on gs = g < tp gs = g < tp ds = < tp (check Fig..1 13
P = fcv α Both transistors are on (Switchg activity Solve for I dsn = I dsp n = p (1 Region A. 0 tn n-device is off, I = ( = I dsn p-device is lear mode = = dsp = 0 0 dsp ( Region B. tn p-device : lear mode n-device : saturation mode [ tn ] µ nε Wn n : I dsn = n, n = ( t L p : gs = ds = ox n 14
( I dsp = p [( tp ( ] gs tp ds µ pε Wp with p = ( t L ox p solve for I dsp = I dsn = n ( tp + ( tp ( tp ( tn p (3 Region C. PMOS, NMOS : saturation I I dsp dsn p = ( n = ( tn tp with I dsp = I dsn + + tp = 1 + tn n p n p by settg n = p and tn = tp we have = : one value only possible N-MOS < gs tn tn < ds 15
P-MOS ( gs > ( tp > ds tp < tp < tn < tp is fixed at, varies make the o/p transition very steep Negative value (4 Region D. < < + tp P-MOS : saturation mode N-MOS : lear mode I I dsp dsn 1 = p ( = [( n tn tp ] solve I dsn = I dsp = p ( tn ( tn ( tp n (5 Region E. + tp p-device off ( n-device is lear mode I = 0 I = 0 = 0 dsp dsn see Table.3 for summary 16
.3.1 n/p ratio ( watch Eq.(.4 n Wn Ln p Wp L p 1. 5 Note T ( T,μ 1.5 T I ds.3. Noise Marg This parameter allows us to determe the allowable noise voltage on the put of a gate so that the put will not be affected. NM H = OH m IH m NM = L ILmax OL max How to determe NM H & NM L 17
IL =.3 IH = 3.3 OL are more difficult (will be discussed later OH (left as your exercise 18
.4 Static Load MOS verters Resistor-load verter Current-source-load verter.4.1 Pseudo-NMOS verter Fast (constant current power-consumg P I but speed 19
0
.6 The Transmission Gate (PMOS (NMOS NMOS pass transistor C load is itially discharged = SS with S=0 ( SS gs = 0 I ds = 0 remas at SS = 5 >, NMOS On = = gs t 0 S=1 ( dd gs = (itially 5 > charge gs = t >, current from to As the put voltage approaches, the n-device begs to turn off tn 1
S=0 (open circuit, remas at tn ( dd, where tn ( dd denotes the t at = (body effect s dd S=1 = 0 = tn ( dd n-device beg to conduct, and fall to ss Transmission of Logic 1 is degraded, ( tn Transmission of Logic 0 is not degraded, ( ss PMOS pass transistor S=1,(S=0 (open = ss = ss S=0 (close =, current to charge (C_load
S=0 (close = ss, = Discharge C_load until through p-device conductg until =, at which pot the transistor stops tp ( ss p-mos passes good 1 p-mos passes poor 0 Transmission gate can pass logic 1 and 0 with degradation! overall behavior (1 S=0 ( S = 1 : N,P devices are OFF = SS, = Z (high impedance =, = Z ( S=1 ( S = 0 : N,P devices are ON = SS, SS =, =, = Used multiplexg element & latch element act as voltage-controlled resistor connectg the put and put Example to analyze a CMOS circuit Way 1=MAN Way =SPICE 3
(1 Capacitor loaded circuit Cload at ss * Cload is large When S is ON NMOS, S = 0 1 PMOS, S = 1 0 Results: Currents of the pass transistor are monitored (transmission gate, gs ( p = 5 (constant current (PMOS It starts at saturation (transmission gate as nonsaturation > gsp tp dsp (NMOS always at saturation, = dsn gsn Rise < gsn tn dsn After, NMOS is off tn 4
Three regions of operation : A N saturation P saturation < tp B N saturation P nonsaturation tp < < tn C N off P nonsaturation tn < a. Region A p : constant current source n : current varies versely with b. Region B both currents vary learly (verse with c. Region C p-current varies verse learly with Charge current amount 5
check : =, SS = SS ( Lightly loaded circuit (Cload is small follows very closely Fig.35(d n-current for = 0. 1 p-current Three regions of operation : a. n (lear, p (off b. n (lear, p (lear c. n (off, p (lear SPICE can be monitored by usg Combed 6