The Devices Jan M. Rabaey
Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-sub-micron effects Future trends
The Diode B A Al SiO2 p n Cross-section of pn-junction in an IC process A Al A p n B B One-dimensional representation Digital Integrated Circuits diode symbol Devices
Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - ρ + x Distance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ 0 -W 1 W 2 x (d) Electrostatic potential.
Diode Current
Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion
Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion
Diode Types p n0 p n (x) x Short-base Diode (standard in semiconductor devices) W n p n (x) Long-base Diode p n0 W n x
Models for Manual Analysis V D + I D = I S (e V D/φ T 1) V D + + I D V Don (a) Ideal diode model (b) First-order diode model
Junction Capacitance
Diffusion Capacitance
Diode Switching Time R src V D V 1 V src I D V 2 t = 0 t = T Excess charge Space charge V D ON OFF ON Time
Secondary Effects 0.1 I D (A) 0 0.1 25.0 15.0 5.0 0 5.0 V D (V) Avalanche Breakdown
Diode Model R S + V D - I D C D
SPICE Parameters
The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor
Cross-Section of CMOS Technology
MOS transistors Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact
Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B
The Threshold Voltage
Current-Voltage Relations S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions
Current-Voltage Relations
Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+
I-V Relation V DS = V GS -V T V GS = 5V I D (ma) 2 1 Triode Saturation V GS = 4V V GS = 3V Square Dependence 0.020 I D 0.010 Subthreshold Current V GS = 2V V GS = 1V 0.0 1.0 2.0 3.0 4.0 5.0 V DS (V) (a) I D as a function of V DS 0.0 V T 1.0 2.0 3.0 V GS (V) (b) I D as a function of V GS (for V DS = 5V). NMOS Enhancement Transistor: W = 100 µm, L = 20 µm
A model for manual analysis
Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B
The Gate Capacitance
Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off
Diffusion Capacitance
Junction Capacitance
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
The Sub-Micron MOS Transistor Threshold Variations Parasitic Resistances Velocity Sauturation and Mobility Degradation Subthreshold Conduction Latchup
Threshold Variations V T Long-channel threshold Low V DS threshold L Threshold as a function of the length (for low V DS ) Drain-induced barrier lowering (for low L)
Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain
Velocity Saturation (1) υn (cm/sec) υ sat = 10 7 constant velocity Constant mobility (slope = µ) µn (cm 2 /Vs) 700 250 µ n0 E sat = 1.5 E (V/µm) 0 E t (V/µm) 100 (a) Velocity saturation (b) Mobility degradation
Velocity Saturation (2) 1.5 0.5 V GS = 5 I D (ma) 1.0 0.5 V GS = 4 V GS = 3 V GS = 2 Linea r Dependence I D (ma) V GS = 1 0.0 1.0 2.0 3.0 4.0 5.0 V DS (V) (a) I D as a function of V DS 0 0.0 1.0 2.0 3.0 V GS (V) (b) I D as a function of V GS (for V DS = 5 V). Linear Dependence on V GS
Sub-Threshold Conduction 10 2 10 4 Linear region ln(i D ) (A) 10 6 10 8 10 10 Subthreshold exponential region 10 12 0.0 V T 1.0 2.0 3.0 V GS (V)
Latchup V DD V DD p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrate n-source R psubs (a) Origin of latchup (b) Equivalent circuit
SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular
MAIN MOS SPICE PARAMETERS
SPICE Parameters for Parasitics
SPICE Transistors Parameters
Fitting level-1 model for manual analysis I D Short-channel I-V curve Region of matching V GS = 5 V Long-channel approximation V DS = 5 V V DS Select k and λ such that best matching is obtained @ V gs = V ds = V DD
Technology Evolution
Bipolar Transistor E B C p + isolation n + p + p n-epitaxy n + p + n + buried layer p-substrate (a) Cross-sectional view. B E n + p n C (b) Idealized transistor structure.
Schematic Symbols and Sign Conventions I B + B + V BC V BE C E + I C V CE I E I B + B + V BC V BE C E + I C V CE I E (a) npn (b) pnp
Operations Modes
Forward Active Operation Carrier Concentration Depletion Regions E B C n b (0) p c0 p e0 n b0 x 0 W W B
Current Components E B C I E 1 I C 2 3 x I B electrons holes
Reverse Active Carrier Concentration E B C n b (W) p e0 n b (0) n b0 0 W p c0 x W B
Saturation Mode Carrier Concentration n b (0) E B C Q A n b (W) p e0 Q S n b0 0 W p c0 x W B
Cutoff Carrier Concentration E B C p e0 n b (0) n b0 n b (W) 0 W p c0 x W B
Bipolar Transistor Operation IC (ma) 0-0.25 I B =25 µa I B =50 µa I B =75 µa I B =100 µa Reverse Operation IC(mA) 15 10 5 Forward Operation Active I B =100 µa I B =75 µa I B =50 µa I B =25 µa -0.5-3.0-1.0 V CE (V) Saturation 0 0.0 2.0 V CE (V)
A Model for Manual Analysis B I B + V BE βfi B C B V BE(on) I B + βfi B C I B = I S (e V BE/φT 1) E E (a) Forward-active (b) Forward-active (simplified) B I B V BE(sat) + C + V CE(sat) E (c) Forward-saturation I C < β F I B
Capacitive Model for Bipolar Transistor C B Q R C bc C cs collector-substrate junction capacitance Q F C be S base charge E base-emitter base-collector junction capacitances
Junction Capacitances
Base Charge - Diffusion Capacitance
Bipolar Transistors - Secondary Effects Early Voltage Parasitic Resistances Beta Variations
Early Voltage I C Saturation Forward Active VBE3 V BE2 V BE1 V A V CE
Parasitic Resistance E B C p + r E n + p + p n + isolation n-epitaxy r B r C1 p + r C3 n + buried layer r C2 p-substrate
Beta Variations ln (I) I KF I C High Level Injection β F Recombination I B V BE (linear)
SPICE models for Bipolar
Main Bipolar Transistor SPICE Models
Spice Parameters for Parasitics
SPICE Transistor Parameters
Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.
Impact of Device Variations 2.10 2.10 Delay (nsec) 1.90 1.70 Delay (nsec) 1.90 1.70 1.50 1.10 1.20 1.30 1.40 1.50 1.60 L eff (in mm) 1.50 0.90 0.80 0.70 0.60 0.50 V Tp (V) Delay of Adder circuit as a function of variations in L and V T