ECE321 Electronics I

Similar documents
MOSFET: Introduction

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

The Devices: MOS Transistors

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

EE5311- Digital IC Design

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

MOS Transistor I-V Characteristics and Parasitics

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

ECE321 Electronics I

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

ECE 497 JS Lecture - 12 Device Technologies

Digital Microelectronic Circuits ( )

Integrated Circuits & Systems

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lecture 3: CMOS Transistor Theory

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

The Devices. Devices

VLSI Design and Simulation

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

ECE321 Electronics I

Lecture 4: CMOS Transistor Theory

MOS Transistor Properties Review

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ECE 342 Electronic Circuits. 3. MOS Transistors

Device Models (PN Diode, MOSFET )

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

Long-channel MOSFET IV Corrections

2.CMOS Transistor Theory

EE 560 MOS TRANSISTOR THEORY

Lecture 5: CMOS Transistor Theory

Device Models (PN Diode, MOSFET )

CMOS Digital Integrated Circuits Analysis and Design

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

MOS Transistor Theory

Lecture 12: MOS Capacitors, transistors. Context

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

FIELD-EFFECT TRANSISTORS

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EE105 - Fall 2005 Microelectronic Devices and Circuits

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D

ECE 546 Lecture 10 MOS Transistors

Introduction and Background

MOS Transistor Theory

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Practice 7: CMOS Capacitance

Conduction in Semiconductors -Review

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Electrical Characteristics of MOS Devices

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

EE382M-14 CMOS Analog Integrated Circuit Design

The Devices. Jan M. Rabaey

Digital Integrated Circuits EECS 312

The Intrinsic Silicon

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Long Channel MOS Transistors

MOSFET Physics: The Long Channel Approximation

Section 12: Intro to Devices

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

EE105 - Fall 2006 Microelectronic Devices and Circuits

Lecture #27. The Short Channel Effect (SCE)

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Practice 3: Semiconductors

Lecture 12: MOSFET Devices

Lecture 010 ECE4430 Review I (12/29/01) Page 010-1

VLSI Design The MOS Transistor

Chapter 4 Field-Effect Transistors

Lecture 04 Review of MOSFET

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

Lecture 11: MOS Transistor

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

University of Toronto. Final Exam

VLSI Design I; A. Milenkovic 1

MOSFET Capacitance Model

ECE520 VLSI Design. Lecture 23: SRAM & DRAM Memories. Payman Zarkesh-Ha

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals

MOS Capacitors ECE 2204

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Transcription:

EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Review of Last Lecture evice Model for Linear Region evice Model for Saturation Region hannel Length Modulation Slide: 1

Threshold Voltage Equation ynamic Parameters of Long hannel MOSET MOSET Parasitic apacitances Overlap capacitances hannel capacitances Junction capacitances Today s Lecture Slide: 3 Threshold Voltage Equation MOSET is a four terminal device; Gate, Source, rain, and Bulk. The Bulk may not be always connected to the Source. Slide: 4

Threshold Voltage Equation We normally assume that the bulk of the MOSET is connected to source. However, sometimes the bulk and source are in different potentials (V SB ). V SB is called body bias. The applied V SB changes the threshold voltage as shown below: V T V T VSB In this equation, V T is the zero bias threshold voltage, ү is the body bias coefficient, and φ is: KT q N Ln ni A Where N A is the doping concentration in the substrate. Slide: 5 Example: Threshold Voltage & Body Bias Assume that V T =.8V, ү=.6 V 1/, φ =.4 V. ind V T if V SB =.5 V V T V T VSB V T.4.5.4.8.55 1. 35.8.6 Observations: 1) Body bias is normally reverse bias. (why?) ) More reverse body bias increases the threshold voltage. Slide: 6 3

MOSET Threshold Voltage Slide: 7 More etail on MOSET Threshold Voltage Zero body bias threshold voltage: V T ms qn A si Q Threshold voltage with body bias: Important acts: Where: V T V Where: KT q T VSB N Ln ni qn Body bias increases threshold voltage Threshold voltage is positive for normal NMOS Threshold voltage is negative for normal PMOS A A si and t Slide: 8 4

MOS apacitance elay of digital MOS circuits depends of capacitance of MOS device There is a trade off between parasitic capacitance and drive strength of MOS device Larger increases the drive strength (I S equation) However, larger increases the device parasitic capacitance MOS parasitic capacitance includes Overlap capacitances hannel capacitances Junction capacitances Between almost every two terminals of MOS device, there is a source of parasitic capacitance Slide: 9 MOS Parasitic apacitances rain G GB B Gate Bulk GS Source SB Slide: 1 5

Overlap apacitances Because of the lateral S/ diffusion, there is an overlap between gate and S/ junctions This overlap capacitance is a constant linear capacitance GSOV GOV W X d L eff Slide: 11 hannel apacitances hannel capacitance is a voltage dependent and non-linear capacitance G G G S G S G S G P-sub Bulk P-sub Bulk P-sub Bulk utoff Region Linear Region Saturation Region Operation Region GBH GSH GH utoff OX WL eff Linear Saturation 1 WL OX eff WL OX eff 3 1 WL OX eff Slide: 1 6

Junction apacitances Junction capacitance is the depletion region capacitance of S/ It is a voltage dependent capacitance (remember reverse biased diode) G S n+ n+ P-sub j 1 V SB j m j A siq NAN NA N 1 KT NAN Ln q ni Slide: 13 Junction apacitance omponents The Junction capacitance of bottom plate is treated separately from the three non-gate edges The gate edge is often ignored since it is part of the conducting channel The bottom plate is usually step graded with m=.5 The sidewall are step graded with m=.33 and face the channel-stop implant which has much higher doping than substrate hannel-stop implant N A+ Side wall W Source N Bottom x j L S Side wall Substrate N A hannel Slide: 14 7

Junction apacitance omponents iff Bottom SW WL Bottom SW J JSW s L W s Slide: 15 MOS Parasitic apacitances G rain GB B GS G GSH GH GSOV GOV Gate Bulk GB GBH SB Sdiff GS Source SB B diff Slide: 16 8