ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines
Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission lines arise? " Lossless Transmission Line " Termination " Lossy Transmission Line 2
Crosstalk 3
Capacitance! There are capacitors everywhere! Already talked about " Wires modeled as a distributed RC network " Parasitic capacitances between terminals on transistor 4
Capacitance Everywhere! Potentially a capacitor between any two conductors " On the chip " On the package " On the board! All wires " Package pins " PCB traces " Cable wires " Bit/word lines 5
Capacitance! decrease with conductor separation! increase with size! depends on dielectric C = ε r ε 0 A d 6
Wire Capacitance! Changes in voltage on one wire may couple through parasitic capacitance to an adjacent wire 7
Crosstalk! A capacitor does not like to change its voltage instantaneously! A wire has high capacitance to its neighbor. " When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. " Called capacitive coupling or crosstalk.! Crosstalk effects " Noise on nonswitching wires " Increased delay on switching wires Slide 8
Qualitative
Driven Wire! What happens to a driven neighbor wire? " One wire switches " Neighbors driven but not switch " What happens to neighbors? 10
Driven Wire! Can this be a problem?! What if neighbor is: " Clock line " Asynchronous control " Non-clock used in synchronous system " Outputs sampled at clock edge 11
Undriven Wire! What happens to undriven wire?! Where do we have undriven wires? 12
Clocked Logic! CMOS driven lines! Clocked logic " Willing to wait to settle! Impact is on delay " May increase delay of transitions 13
Quantitative
Wire step response! Step response for isolated wire? 15
Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? 16
Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt 17
Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt d(v C 1 (t) V 2 (t)) 1 dt dv C 1 (t) 1 = C 2 dv 2 (t) dt = (C 1 + C 2 ) dv (t) 2 dt dt C 1 V 1 (t) = (C 1 + C 2 )V 2 (t) V 2 (t) = C 1 C 1 + C 2 V 1 (t) 18
SPICE C 1 =10pF, C 2 =20pF 19
Good (?) Capacitance! High capacitance to ground plane " Limits node swing from adjacent conductors V 2 = " C $ 1 # C + C 1 2 % ' V & 1 20
Driven Adjacent Wire! What happens when neighbor line is driven? 21
Driven Adjacent Wire! What happens when neighbor line is driven? " Recovers with time constant: R 2 (C 1 +C 2 ) 22
Spice: R 2 =1K, C 1 =10pF, C 2 =20pF diversion 23
Magnitude of Noise on Driven Line! Magnitude of diversion depends on relative time constants " τ 1 << τ 2 " full diversion, then recover " τ 1 >> τ 2 " Drive capacitor faster than line 1 can change " τ 1 ~= τ 2 " little noise " Somewhere in between 24
Spice: C 1 =1pF, C 2 =2pF 25
Switching Line with Finite Drive! What impact does the presence of the non switching line have on the switching line? " All previous questions were about non-switching " Note R on switching 26
Simultaneous Transition! What happens if lines transition in opposite directions? 27
Simultaneous Transition! What happens if transition in opposite directions? " Must charge C 1 by 2V " Or looks like 2C 1 between wires 28
Simultaneous Transition! What happens if lines transition in same direction? 29
Simulation! V 2 switching at ¼ frequency of V 1! No crosstalk reference case where no V 2 30
Simulation Setup V1 V2 C1 C2 C2 31
Crosstalk Simulation 1.3ns 1.8ns 2.8ns 32
Crosstalk Simulation 1.3ns 1.8ns 2.8ns 33
Crosstalk Simulation 1.3ns 1.8ns 2.8ns 34
Where Does it Arise? 35
Cables and PCB Wires Source; http://en.wikipedia.org/wiki/file:flachbandkabel.jpg 36
Printed Circuit Board Source: http://en.wikipedia.org/wiki/file:testpad.jpg 37
Interconnect Cross Section 38
Standard Cell Area inv nand3 All cells uniform height Cell area Width of channel determined by routing Penn ESE 570 Spring 2018 - Khanna 39
Noise Implications! So what if we have noise?! If the noise is less than the noise margin, nothing happens! Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes " But glitches cause extra delay " Also cause extra power from false transitions! Dynamic logic never recovers from glitches " Can t correct mid-cycle, need precharge! Memories and other sensitive circuits also can produce the wrong result (i.e faults) Slide 40
Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: Slide 41
Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer w Delay (ns): RC/2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 1500 2000 s Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 1500 2000 Pitch (nm) Wire Spacing (nm) 320 480 640 l t h Slide 42
Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer " Shielding Delay (ns): RC/2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 500 1000 1500 2000 Pitch (nm) Coupling: 2C adj / (2C adj +C gnd ) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 500 1000 1500 2000 Pitch (nm) Wire Spacing (nm) 320 480 640 vdd a 0 a 1 gnd a 2 a 3 vdd vdd a 0 gnd a 1 vdd a 2 gnd a 0 b 0 a 1 b 1 a 2 b 2 Slide 43
Repeaters in Wiring
Reminder: Wire Delay! Wire N units long: =R unit *C unit *N 2 /2! With R wire = N R unit C wire = N C unit " R unit =1kΩ " C unit =1pF Penn ESE 570 Spring 2018 - Khanna 45
Interconnect Buffering! RC (on-chip) Interconnect Buffering 46
Delay of Wire! Long Wire: 1mm! R u = 60K Ω per 1mm of wire! C u = 0.16 pf per 1mm of wire! Driven by buffer " R buf = 25K Ω " C self = 0.02 ff " C g = 0.01fF! Loaded by identical buffer 47
Formulate Delay Delay of buffer driving wire? 48
Formulate Delay Delay of buffer driving wire? R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 49
Calculate Delay! C load =! R buf =! C self =! C wire =! R wire = R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 50
Calculate Delay! C load = 2 C g =.02fF! R buf = 25K Ω! C self = 0.02fF! C wire = L*C u =.16pF! R wire = L*R u = 60K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 51
Calculate Delay! C load = 2 C g =.02fF! R buf = 25K Ω! C self = 0.02fF 8.8ns! C wire = L*C u =.16pF! R wire = L*R u = 60K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 4ns + 4.8ns +1.2ps 52
Buffering Wire 53
Buffering Wire: L/2! C load =! R buf =! C self =! C wire =! R wire = 54
Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω 55
Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 2ns +1.2ns +.6 ps = 3.2ns 56
Buffering Wire: L/2! C load = 2 C g =.02fF! R buf = 25K Ω! C self =.02fF 6.4ns! C wire = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 2ns +1.2ns +.6 ps = 3.2ns 57
Buffering Wire: L/N Wire of Length Delay (ns) Number in 1mm Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm 10 0.01 mm 100 0.001 mm 1000 R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 58
Buffering Wire: L/N Wire of Length Delay (ns) Number in 1mm (N) Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm 0.45ns 10 4.5ns 0.01 mm.041ns 100 4.1ns 0.001 mm.005ns 1000 5ns R buf ( C self + C wire + C ) load + 0.5R wire C wire + R wire C load 59
N Buffers! Delay Equation for N buffers? N R buf C self + C wire N +C load + 0.5 R wire N C wire N + R wire N C load 60
Minimize Delay! Minimize delay! Derivative with respect to N and solve for 0 N R buf ( C self +C ) load + R buf C wire + 0.5 1 N 0 = R ( buf C self +C ) load 0.5 1 N 2 R wire C wire + R wire C load R wire C wire N = R buf 0.5R wire C wire ( C self +C ) load 61
Minimize Delay Equalizes delay in buffer and wire N = R buf 0.5R wire C wire C self + C load ( ) N R buf ( C self + C ) + R C + 0.5! load # 1 buf wire " N $ &R wire C wire + R wire C load % 62
Delay with Optimal N R buf 0.5R wire C wire C self + C load ( ) R buf ( C self + C load ) + R buf C wire + 0.5 0.5R wire C wire R buf ( C self + C load )! # # " R buf ( C self + C load ) 0.5R wire C wire $ & & R C + R C wire wire wire load % ( ) + R buf C wire + 0.5R wire C wire ( R buf ( C self + C load )) + R wire C load 2 0.5R wire C ( wire R ( buf C self + C )) load + R buf C wire + R wire C load 63
Segment Length! R wire = L R unit! C wire = L C unit * L seg = L N # R N = 0.5% wire C wire % $ R buf C self + C load ( ) & ( ( ' * L seg # R N = L 0.5% u C u % $ R buf C self + C load ( ) = L " N = 2 R buf C self + C load $ # R u C u & ( ( ' ( ) % ' & 64
Optimal Segment Length! Delay scales linearly with distance once optimally buffered * L seg = L # N = 2 R buf C self + C % load % R u C $ u ( ) & ( ( ' # N = L 0.5% % $ R u C u ( ) R buf C self + C load & ( ( ' 65
Buffer Size?! How big should buffer be? " R buf = R un /W " C self = 2 W C dff = 2 W γ C g " C load = 2 W C g 66
Buffer Size?! How big should buffer be? " R buf = R un /W " C self = 2 W C dff = 2 W γ C g " C load = 2 W C g 2 0.5R wire C ( wire R ( buf C self + C )) load + R buf C wire + R wire C load! R 2 0.5R wire C un wire # W 2WC g 1+γ " ( ( )) $ & + R un % W C wire + R wire 2WC g 2 0.5R wire C ( wire 2R un C ( g 1+γ) ) + R un W C wire + R wire 2WC g 67
Implication on Buffer Size - W! R wire = L R unit! C wire = L C unit 2 0.5R wire C ( wire 2R un C ( g 1+γ) ) + R un W C + R 2WC wire wire g 0 = 2R wire C g R un C wire 1 W 2 W = R un C wire 2R wire C g =! # W independent of Length " Depends on technology R un C unit 2R unit C g 68
Delay at Optimum W 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un W C + R 2WC wire wire g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un R un C wire 2R wire C g C wire + R wire 2 R un C wire 2R wire C g C g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + R un C wire 2R wire C g + R un C wire 2R wire C g 2 0.5R wire C ( wire 2R un C g ( 1+γ) ) + 2 2R un C g C wire R wire 69
Delay at Optimum W! If γ=1 2 R wire C ( wire R un C g ( 1+1) ) + 2 2R un C g C wire R wire 2 2R un C g C wire R wire + 2 2R un C g C wire R wire 4 2R un C g C wire R wire! Optimal design equalizes all delays! 70
Where Transmission Lines Arise 71
Transmission Lines! Cable: coaxial! PCB " Strip line " Microstrip line! Twisted Pair (Cat5) 72
Transmission Lines! This is what wires/cables look like " Aren t an ideal equipotential " Signals do take time to propagate " Maintain shape of input signal " Within limits " Shape and topology of wiring effects how signals propagate! Need theory/model to support design " Reason about behavior " Understand what can cause noise " Engineer high performance/speed communication 73
Wire Formulation 74
Wires! In general, our wires have distributed R, L, C components 75
RC Wire! When R dominates L " We have the distributed RC Wires " Typical of on-chip wires in ICs 76
Lossless Transmission Line! When resistance is negligible " Have LC wire = Lossless Transmission Line " No energy dissipation (loss) through R s " More typical of Printed Circuit Board wires and bond wires 77
Intuitive: Lossless! Pulses travel as waves without distortion " (up to a characteristic frequency) 78
SPICE Simulation 79
Step Response SPICE 80
Pulse Response SPICE 81
Contrast RC Wire 82
Contrast 83
Model! Now voltage is a function of time and position " Position along wire distance from source! Want to get V(x,t) " And I(x,t) 84
Implication " Wave equation: " Solution: 2 V x = LC 2 V t V(x,t) = A + Be x wt " What is w? Be x wt = LCw 2 Be x wt w = 1 LC w is the rate of propogation 85
Propagation Rate in Example! L=1uH! C=1pF! What is w? w = 1 LC 86
Signal Propagation 87
Signal Propagation Delay linear in length 88
Contrast RC Wire RC wire delay quadratic in length.5r un C un N 2 89
Impedance! Transmission lines have a characteristic impedance Z 0 = L C 90
Infinite Lossless Transmission Line! Transmission line looks like resistive load Z 0 = L C Z 0! Input waveform travels down line at velocity " Without distortion w = 1 LC 91
Termination
End of Line! What happens at the end of the transmission line? 93
Analyze End of Line! Incident Wave, Reflected Wave, Transverse Wave 94
End of Line! What happens at the end of the transmission line? " Short Circuit, R=0 " Hint: what must happen in steady state? " Terminate with R=Z 0 " Open Circuit, R= 95
Reflection Reflection coefficient # R Z V 0 i % $ R + Z 0 & ( = V ' r 96
Analyze End of Line! V i +V r =V t " R Z V 0 % i $ ' = V r # R + Z 0 & " R Z V 0 % i $ ' = V t V i # R + Z 0 & " R Z V 0 % i $ +1' = V t # R + Z 0 & V i " 2R % $ ' = V t # R + Z 0 & Transmission coefficient 97
Open # R Z V 0 & i % ( = V $ R + Z r 0 ' 98
Terminate R=Z 0 # R Z V 0 & i % ( = V $ R + Z r 0 ' 99
Short # R Z V 0 & i % ( = V $ R + Z r 0 ' 100
Longer LC (open)! 40 Stages! L=100nH! C=1pF w = 1 LC = c 0 Stage delay? How long to propogate? ε r µ r! Drive with 2ns Pulse! No termination (open circuit) " What reflection do we expect? 101
Pulse Travel RC! V1,V3,V4,V5,V6 about 10 stages apart 102
Visualization! http://www.williamson-labs.com/xmission.htm Matched Open Short 103
Back to Source 104
Back at Source?! What happens at source? " Depends on how it s terminated 105
R Z 0! What happens? " 75 Ω termination on 50 Ω line 106
Transmission Line Symbol! Specify delay of full Tline and characteristic impedance! Need reference 107
Simulation! For these, with direct drive from voltage source " Source looks like short circuit (not typical of CMOS) " Source cannot be changed 108
50Ω line, 75Ω termination # R Z V r = V 0 i % $ R + Z 0 & # 75 50& ( = V i % ( = 0.2V ' $ 75 + 50' i 109
Source Series Termination! What happens here? 110
Simulation 111
Series Termination! R series = Z 0! Initial voltage divider " Half voltage pulse propogates down Tline! End of line open circuit " Sees single transition to full voltage (full reflection)! Reflection returns to source and sees termination R series = Z 0! No further reflections 112
CMOS Driver / Receiver! Driver: What does a CMOS driver look like at the source? " I d,sat =1200µA/µm @ 45nm, V dd =1V! Receiver: What does a CMOS inverter look like at the sink? 113
CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat =1200µA/µm @ 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ 114
CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat =1200µA/µm @ 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ " W=370 " I drive =1200µA/µm*45nm*370=20mA " R out =V dd /I drive =50Ω 115
CMOS Receiver! Receiver: What does a CMOS inverter look like at the sink? 116
Lossy Transmission Line! How do addition of R s change? " Concretely, discretely think about R=0.2Ω every meter on Z 0 =100Ω " what does each R do? 117
Lossy Transmission Line! Each R is a mismatched termination! Each R is a voltage divider " 2(R + Z ) V = V 0 t i $ #(R + Z ) + Z 0 0 " Z V = V 0 i+1 t $ # R + Z 0 % ' & % ' & 118
Lossy Transmission Line " 2(R + Z ) V = V 0 i+1 i $ #(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 % ' & "" 2(R + Z ) V = V $ 0 snk src $ ##(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 %% '' && N 119
Lossy Transmission Line! How long before drop voltage by half? R=0.2Ω every meter on Z 0 =100Ω "" 2(R + Z ) V = V $ 0 snk src $ ##(R + Z ) + Z 0 0 %" ' $ &# Z 0 R + Z 0 %% '' && N 120
Idea! Capacitance is everywhere, especially between adjacent wires, and will get noise from crosstalk " Clocked and driven wires " Slow down transitions " Undriven wires voltage changed " Can cause spurious/false transitions! Wire delay linear once buffered optimally " Optimal buffering equalizes delays " Buffer delay, Delay on wire between buffers, Delay of wire driving buffer! Transmission lines " high-speed " high throughput " long-distance signaling! Termination 121
Admin! Tania extra office hours " Monday 1-3pm! Tuesday (last) lecture " Details about final exam " Review for final exam 122