EE4-Fall 2000 Digital Integrated ircuits Lecture 6 Inverter Delay Optimization Announcements Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday Homework #4 due next Thursday 2 2
lass Material Last lecture Overview of Semiconductor Memory Today s lecture Inverter Delay Optimization Reading (5.4, 5.5) 3 3 Inverter hain In Out L For some given L : How many stages are needed to minimize delay? How to size the inverters? Anyone want to guess the solution? 4 4
areful about Optimization Problems Get fastest delay if build one very big inverter So big that delay is set only by self-loading Likely not the problem you re interested in Someone has to drive this inverter 5 5 Engineering Optimization Problems in General eed to have a set of constraints onstraints key to: Making the result useful Making the problem have a clean solution For sizing problem: eed to constrain size of first inverter 6 6
Delay Optimization Problem # You are given: A fixed number of inverters The size of the first inverter The size of the load that needs to be driven Your goal: Minimize the delay of the inverter chain eed model for inverter delay vs. size 7 7 Inverter Delay Minimum length devices, L = 0.09µm Assume that for W P = 2W = 2W approximately equal resistances, R = R P approx. equal rise and fall delays, t phl = t plh Analyze as an R network: L L R = R R = R = R P sq, p sq, n W WP W 2W W Delay: t phl = (ln 2) R L = t plh = (ln 2) R p L Loading on the previous stage: in = 3W g 8 8
Inverter Delay P = 2W g W 2W int L R W = Rsq, n = L W W int 3 d in = 3W g = W g Replace ln(2) with k (a constant): Delay = kr W int + kr W L Delay = kr sq,n (L/W)(3W d ) + kr sq,n (L/W) L 9 9 Inverter with Load P = 2W g 2W Delay W int L = W g Load Delay = kr W in ( int / in + L / in ) = 3kLR sq,n g [ d / g + L /(3W g )] = Delay (Internal) + Delay (Load) 0 0
Delay Formula ( + ) Delay ~ R W int L ( / ) ( γ ) t = kr + = t + f p W in int in L in inv int = γ in (γ for inverter) f = L / in electrical fanout R W = R sq (L /W) ; in =3W g t inv = 3 ln(2) L R sq g t inv is independent of sizing of the gate!!! Apply to Inverter hain In Out 2 L t p = t p + t p2 + + t p t pj = tinv γ + in, j+ in, j 2 2 t t t in, j+ p = p, j = inv γ +, in, + = L j= i= in, j
Optimal Tapering for Given Delay equation has - unknowns, in,2 in, To minimize the delay, find - partial derivatives: t =... + t + t +... in, j in, j+ p inv inv in, j in, j dt = = 0 d p in, j+ tinv tinv 2 in, j in, j in, j 3 3 Optimal Tapering for Given (cont Result: every stage has equal fanout: = in, j in, j+ in, j in, j = in, j in, j in, j + (cont d) In other words, size of each stage is geometric mean of two neighbors: Equal fanout every stage will have same delay 4 4
Optimum Delay and umber of Stages When each stage has same fanout f : f = F = / L in, Effective fanout of each stage: f = F Minimum path delay: p inv ( γ ) t = t + F 5 5 Example In f f 2 Out L = 8 L / has to be evenly distributed across = 3 stages: f = 3 8 = 2 6 6
Delay Optimization Problem #2 You are given: The size of the first inverter The size of the load that needs to be driven Your goal: Minimize delay by finding optimal number and sizes of gates So, need to find that minimizes: ( γ ) t = t + p inv L in 7 7 Solving the Optimization Rewrite in terms of fanout/stage f: f L in ln ( ) (( ) / γ ) ln ( ) f + γ tp = tinv L in + = tinv L in ln f t p ln f γ f = tinv ln ( L in ) = 0 2 f ln f f = = = exp + ( γ f ) For γ = 0, f = e, = ln ( L / in ) 8 8 L ln f in
Optimum Effective Fanout f Optimum f for given process defined by γ 5 f = exp + ( γ f ) 4.5 f opt 4 3.5 e 3 f opt = 3.6 for γ = 2.5 0 0.5.5 2 2.5 3 9 9 γ In Practice: Plot of Total Delay [Hodges, p.28] urves very flat for f > 2 Simplest/most common choice: f = 4 20 20
ormalized Delay As a Function of F t = t ( γ + F), F = p inv L in Textbook: page 20 (γ = ) 2 2 Buffer Design f t p 64 64 65 8 64 2 8 8 4 6 64 3 4 5 2.8 8 22.6 64 4 2.8 5.3 22 22
What About Energy (and Area)? Ignoring diffusion capacitance: tot = in + f in + + f in = in ( + f + + f ) = in + in f + in f ( + f + + f -2 ) Overhead!!! f(f - -) / (f-) Example (γ=0): L = 20pF; i = 50fF = 6 Fixed: 20pF Overhead:.66pF!!! 23 23 Example Overhead umbers Example: L = 20pF; in = 50fF 25 40 Overhead apacitance (pf) 20 5 0 5 35 30 25 20 Delay (t inv ) 0 2 3 4 5 6 7 8 9 0 5 umber of Stages 24 24
ext Lecture Gate Delay Logical Effort 25 25