SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s 18-322 slides (CMU), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UC).
SLIDE 2 Overview General complementary logic design, perspective, stick-figure circuit diagrams Examples: constructing PDN/PUN duals, logic -> circuit, circuit -> logic, circuit -> layout, layout -> circuit, cross sectional views of layout
SLIDE 3 Complementary Design VDD Dual networks Pull-up Network (pfet network) INPUT/S OUTPUT Pull-down Network (nfet network) PMOS Pull-Up Network (PUN) NMOS Pull-Down Network (PDN)
Why Division? S V DD VDD SLIDE 4 D 0 V DD C L V DD D C L V DD 0 S PMOS will pass a 1 NMOS will pass a 0
SLIDE 5 Why Division? V DD V DD D VDD V Tn V GS S 0 V DD - V Tn C L V GS S C L V DD V Tp D V Tp NMOS will not pass a 1 PMOS will not pass a 0
SLIDE 6 uilding locks NMOS devices in series implement a NND function output = NMOS devices in parallel implement a NOR function output = +
Implements rbitrary Logic SLIDE 7 Pull-Up Network: on when function = 1 Pull-Down Network: on when function = 0
SLIDE 8 Static CMOS: Perspective Static as in output is logic function of inputs, and, given stable inputs, it does not change over time Propagation delay function of load capacitance and resistance of transistors PROS: Full rail-to-rail swing; high noise margins Logic levels not dependent upon relative device sizes lways a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation CONS: N inputs => 2N transistors in design
Constructing the Dual x x SLIDE 9 y y Transistors in parallel are in series in dual; transistors in series are in parallel in dual This is the physical realization of DeMorgan s theorems: + = [!( + ) =!! or!( ) =! &!] = + [!( ) =! +! or!( & ) =!!]
SLIDE 10 Examples Constructing the Dual VDD C E D OUT
SLIDE 11 Examples Constructing the Dual OUT D C
Examples: Logic <-> Circuit XOR [ out = ~( + ) ] SLIDE 12
SLIDE 13 Examples: Logic <-> Circuit XOR [ out = ~( + ) ] VDD OUT
Examples: Logic <-> Circuit out = ~( ( C + D )) SLIDE 14
SLIDE 15 Examples: Logic <-> Circuit out = ~( ( C + D )) VDD D C OUT C D
SLIDE 16 SCMOS SCLLE DESIGN RULES CMOS Scales Well Exploit That Fact Implement it now, shrink it later Express all design rules in terms of unit dimension Change dimension of the unit, whole design shrinks Mead & Conway Unit Dimension: Minimum Line Width (2λ) In 1978, λ = 1.5 µm (a.k.a. 3 micron technology) In 2004, λ = 0.045 µm (a.k.a. 90 nanometer technology) Important Intellectual Idea (but not used in industry) (but we will) (why not? elegance costs $$$ currently thousands of design rules)
How lambda is used SLIDE 17
Layout <-> Circuit SLIDE 18 magenta blue red green yellow black Metal 2 Metal 1 Polysilicon (gate material) ctive area (n+ or p+ diffusion) Well (p or n) Contact (via)
Layout <-> Circuit SLIDE 19 FETs in series: source-drain overlap FETs in parallel: can share source/drain
Layout <-> Circuit 2-INPUT NND SLIDE 20 FETs in series (in NND PDN): source-drain overlap FETs in parallel (in NND PUN): share drain
Layout <-> Circuit How bout 2-INPUT ND? SLIDE 21
Layout <-> Circuit How bout 2-INPUT ND? SLIDE 22 dd an inverter at the end
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 23 Let s look at two equivalent approaches
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 24
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 25
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 26
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 27 nother design of same gate (circuit above simply flipped)
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 28
Examples: Layout <-> Circuit NOT LL LYOUTS RE CRETED EQUL SLIDE 29
SLIDE 30 Examples: Layout <-> Circuit Gate Design Procedure Run VDD & GND in metal at top & bottom Run vertical poly for each gate input Order gates to allow maximum source-drain abutting Place max # n-diffusions close to GND Place max # p-diffusions close to VDD Make remaining connections with metal (try to minimize metal usage)
SLIDE 31 Stick Diagrams Introduced by Mead & Conway in 80 s Every line of conduction-material layer is represented by line of distinct color Polysilicon (gate) ctive (n+ or p+) Metal 1 n-well boundary contact (via) nfet nfet VDD OUT GND D C
Stick Diagrams SLIDE 32
Stick Diagrams SLIDE 33
Stick Diagrams SLIDE 34
Stick Diagrams SLIDE 35
Stick Diagrams SLIDE 36
Stick Diagrams SLIDE 37
SLIDE 38 Examples 2-input NND VDD output
SLIDE 39 Examples 2-input NND VDD OUT GND
SLIDE 40 Examples 4-input NOR VDD C D output C D
SLIDE 41 Examples 4-input NOR VDD OUT GND C D
Examples out = ~( ( C + D )) SLIDE 42
SLIDE 43 Examples out = ~( ( C + D )) VDD D C OUT C D
SLIDE 44 Examples out = ~( ( C + D )) VDD OUT GND C D OOOPS -- can t do this
SLIDE 45 Examples out = ~( ( C + D )) VDD OUT GND D C
SLIDE 46 Examples out = ~( ( C + D )) VDD OUT GND D C For PUN, either re-route poly or cut p-diff
Views of a Design SLIDE 47 2D top-down view (how designers see the chip) 3D cross section (how process engineers see the chip)
SLIDE 48 Examples poly metal VDD active n-well via a b n-well GND OUT
SLIDE 49 Examples poly VDD metal active n-well n-well OUT Y via a b GND W X Z
SLIDE 50 Sizing: What is a MOSFET? resistor: 1 L R n = --------------------------------------------- µ n C ox ( V GS V Tn ) W ---- (among other things...) Increasing W decreases the resistance; allows more current to flow Oxide capacitance C [F/cm 2 ox = ε ox t ox ] W Transconductance β n = µ n C ox ---- L = k' W ---- n L Gate capacitance = C ox WL [F] C G
SLIDE 51 nfet vs. pfet 1 W R n = ------------------------------------ β β n ( V DD V Tn ) n = µ n C ox ---- L 1 W R p = --------------------------------------- β β p ( V DD V Tp ) p = µ p C ox ---- L n p µ n ----- r µ p = Typically (2.. 3) (µ is the carrier mobility through device)
Transistor Sizing I W 2W SLIDE 52 Source L Drain L The electrical characteristics of transistors determine the switching speed of a circuit Need to select the aspect ratios (W/L) n and (W/L) p of every FET in the circuit Define Unit Transistor (R 1, C 1 ) L/W min -> highest resistance (needs scaling) R 2 = R 1 2 and C 2 = 2 C 1 Separate nfet and pfet unit transistors Unit devices are not restricted to individual transistors
Sizing I: Complex Gates Critical transistors: those in series VDD SLIDE 53 2 nets in series: scale each by 2x C E Two devices in series: scale each by 2x D OUT N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square
Sizing I: Complex Gates Critical transistors: those in series VDD SLIDE 54 2x1 2x1 2 nets in series: scale each by 2x C 4x1 2x1 E Two devices in series: scale each by 2x D 4x1 OUT N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square
SLIDE 55 Examples VDD C E D OUT E C D
SLIDE 56 Examples VDD 2 2 C VDD 6 6 12 6 E C 4 2 E D 12 2 2 OUT E D 4 OUT 2 C 2 2 ssuming Wp = 3Wn D 2 2 E 2 C 2 2 D
Examples VDD C SLIDE 57 D C OUT D C
Examples VDD 6 6 6 C SLIDE 58 18 6 D C 18 18 OUT D 2 3 3 2 2 2 3 C