DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 Solution - Final am (Online Section) (Due Date: December th by : am) Clarity i very important! Show your procedure! PROBLM (2 PTS) Complete the timing diagram of the following circuit. 3 2 D D D D D
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM 2 ( PTS) We want to deign a counter modulo-9 with enable uing a State Machine. The counter mut aert an output = when the maimum count i reached. Provide the State Diagram (any repreentation) and the citation table. I thi a Moore or a Mealy machine? = '' = = = = = S =,= = S2 = =,= =2,= = S = =3,= S5 =,= = = S9 =8,= = = S8 = =7,= = S7 =6,= = = S6 =5,= = PRSNT STAT NXT STAT PRSNT STAT 3 2 (t) NXTSTAT 3 2 (t+) S S2 S S5 S6 S7 S8 S9 S S2 S S5 S6 S7 S8 S9 MOOR MACHIN S S2 S S5 S6 S7 S8 S9 S2 S S5 S6 S7 S8 S9 S X X X X X X X X X X X X X X
ILUT OLUT DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM 3 (5 PTS) Given the following ytem, complete the Timing Diagram. The LUT 8-to-8 implement the following function: DI 8 D 8 8 LUT 8-to-8 DO O 8 DATA ceil(qrt(25))= 6 ceil(qrt(235))= 6 ceil(qrt(25)) = 5 ceil(qrt())= 7 O DATA FA B 9 5 2C 7 DI DO FA B 9 2C 5 7
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM (8 PTS) Provide the State Diagram (any repreentation) of the FSM whoe VHDL decription i hown below. Complete the Timing Diagram. library ieee; ue ieee.td_logic_6.all; entity circ i port (, : in td_logic; a, b: in td_logic;,w,: out td_logic); end circ; S a = architecture behavioral of circ i type tate i (S, S2, ); ignal y: tate; begin Tranition: proce (,, a, b) begin if = '' then y <= S; elif ('event and = '') then cae y i when S => if a = '' then if b = then y <= S2; ele y <= S; end if; ele y <= S; end if; b S2 a b w when S2 => if a = '' then y <= ; ele y <= S; end if; when => if b = '' then y <= ; ele y <= S; end if; end cae; end if; end proce; Output: proce (y,a,b) begin <= ; w <= ; <= ; cae y i when S => if a = and b = then <= ; end if; when S2 => <= ; when => if b = then w <= ''; end if; end cae; end proce; end behavioral; clock a b tate S S S S S S S S2 S S S S2 w
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM 5 ( PTS) Sequence detector (with overlap): Draw the tate diagram (in ASM form) of a circuit (with an input ) that detect the following equence:. The detector mut aert and output = when the equence i detected. S = S2 S S5 S6 S7
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM 6 (5 PTS) Baic Proceor: Available Regiter: R (regiter, bit), R(regiter, bit), PC (program counter, bit), OUT (output regiter, bit) IR (intruction regiter, 8 bit) Intruction Memory: Store up to 6 8-bit intruction. Intruction Set: Intruction are pecified on the Intruction Regiter (IR): IR: OPCOD DR SR IMMDIAT DATA DR= R i the detination regiter, DR= R i the detination regiter. SR= R i the ource regiter, SR= R i the ource regiter. OPCOD (IR[7..5]) Intruction Operation MOV DR, SR DR SR LOADI DR, DATA DR DATA, DATA = IR[3..] ADD DR, SR DR DR + SR ADDI DR, DATA DR DR + DATA, DATA = IR[3..] SR DR, SR DR &SR[3..] IN DR DR IN OUT DR OUT DR JNZ DR, ADDRSS PC PC + if DR= PC IR[3..] if DR * ADDRSS = IR[3..] Write an aembly program for a counter from 2 to 3: 2,3,, 3,2,3, The count mut be hown on the output regiter (OUT). Ue label to pecify any addre where your program jump. Note that you can have only up to 6 intruction. Provide the content of the Intruction Memory. addre INSTRUCTION MMORY tart: loadi R,2 loadi R, loop: out R OUT: how the count addi R, addi R, jn R, loop loadi R, jn R, tart
DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-238L: Computer Logic Deign Fall 23 PROBLM 7 (2 PTS) Complete the timing diagram of the following digital circuit that include an FSM (in ASM form) and a datapath circuit. data S = clr + p clr S2 p clr clr: ynchronou clear If =clr=, then = clr clock FINIT STAT MACHIN done done clock data p clr tate S S S2 S2 S2 S2 S2 S2 S S S2 S2 S2 S2 S2 S2 done