EE241 - Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low Power-Low Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks - 3/7 by 5pm 1
Principles of Power Reduction P ~ α + a - switching probability C L load capacitance V swing voltage swing f - frequency ( C V + I t ) L swing ( I DC + I Leak ) V DD SC SC V DD I sc mean value of switching transient current t sc short current time I DC static current I leak leakage current f Dominant: P ~ α C L V swing V DD f Kuroda, Sakurai, IEICE 4/95 Principles of Power Reduction P ~ α C V V f E ~ α CL Vswing VDD L swing DD Reducing switching probability (α)» Architectures» Power simulators/estimators (time consuming)» Glitching power reduction (15-2%) Reducing load capacitance» Technology scaling» Gate sizing, minimization, interconnect, CAD» Circuit techniques (PTL, ) Reducing supply voltage» Quadratic impact on power» Impact on delay how to maintain throughput? Reducing frequency 2
Trends in Power Dissipation Processor Power 1 Max Power (Watts) 1 486 Pentium II (R) Pentium Pro (R) Pentium(R) 486 Pentium(R) MMX? 1 386 386 1.5m 1m.8m.6m.35m.25m.18m.13m ➊ Lead processor power increases every generation ➋ Compactions provide higher performance at lower power 3
If We Sustain Die Size Trend 1, Die size (mils) 1, Pentium (R) Pentium Pro 62 (R) 2166 486 64 21164 386 2164A 61 63 1 1985 199 1995 2 25 21 di/dt in AU 1.E+8 1.E+7 1.E+6 1.E+5 1.E+4 1.E+3 1.E+2 1.E+1 1.E+ Pentium Pro (R) Pentium (R) 486 386 1.5m.8m.35m.18m.1m 1, 1, Power (Watts) 1, 1 Pentium Pro (R) 1 Pentium (R) 486 386 1 1985 199 1995 2 25 21 1, Icc (amps) 1 1 1 Pentium Pro (R) 486 386 Pentium (R) 1985 199 1995 2 25 21 Portability BATTERY (4+ lbs) Multimedia Terminals Laptop Computers Digital Cellular Telephony Nominal Capacity (Watt-hours / lb) 5 4 3 2 1 Rechargable Lithium Nickel-Cadium Ni-Metal Hydride 65 7 75 8 85 9 95 Year Expected Battery Lifetime increase over next 5 years: 3-4% 4
Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors Dynamic Power Consumption V dd E ->1 = C L V dd 2 PMOS i supply A 1 NETWORK A N NMOS NETWORK Vout CL E 1 T T Vdd = Pt ()dt = V dd i supply ()dt t = V dd C L dv out = C L V 2 dd T T Vdd E = P ()dt t cap = V i ()dt t cap = C V dv out cap = 1 - C V 2 L out out 2 L dd 5
Modification for Circuits with Reduced Swing V dd V dd V dd -V t C L E 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory) Dynamic Power Consumption - Revisited Power = Energy/transition * transition rate = C L * V dd 2 * f 1 = C L * V dd 2 * P 1 * f = C EFF * V dd 2 * f Power Dissipation is Data Dependent Function of Switching Activity C EFF = Effective Capacitance = C L * P 1 6
Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E = C V 2 nn ( ) N L dd E N : the energy consumed for N clock cycles n(n ): the number of ->1 transition in N clock cycles P = lim avg N E N -------- f N clk = nn ( ) lim ------------ N N C L V 2 fclk dd α 1 = nn ( ) lim ------------ N N P = α avg 1 C L V 2 fclk dd Type of Logic Function: NOR vs. XOR 7
Type of Logic Function: NOR vs. XOR Transition Probabilities P ->1 (NOR,NAND) = (2 N -1)/2 2N P ->1 (XOR) = 1/4 8
Transition Probabilities for Basic Gates Transition Probability of 2-input NOR Gate 9
How about Dynamic Circuits? V DD φ M p Out In 1 In 2 In 3 PDN φ M e Power is Only Dissipated when Out=! C EFF = P(Out=).C L 2-input NAND Gate Example: Dynamic 2 Input NOR Gate Assume: P(A=1) = 1/2 P(B=1) = 1/2 Then: P(Out=) = 3/4 C EFF = 3/4 * C L Switching Activity Is Always Higher in Dynamic Circuits 1
Type of Logic Style: Static vs. Dynamic V dd V dd A CLK B A B C L A B C L CLK Power is only dissipated when Out=! STATIC NOR DYNAMIC NOR α ->1 = 3/16 N α = ------- 1 2 N = 3-4 Transition Probabilities for Dynamic Gates Switching Activity for Precharged Dynamic Gates P 1 = P 11
Another Logic Style: Dynamic DCVSL Vdd Vdd OUTB IN INB I OUT I Guaranteed transition for every operation! α ->1 = 1 Problem: Reconvergent Fanout A X B Z Reconvergence P(Z=1) = P(B=1). P(X=1 B=1) Becomes complex and intractable real fast 12
Glitching in Static CMOS also called: dynamic hazards A B X C Z ABC 11 X Z Unit Delay Observe: No glitching in dynamic circuits Example 1: Chain of NOR Gates 1 out1 out2 out3 out4 out5... 6. V (Volt) 4. 2. out8 out2 out4out6 out1 out3 out5 out7. 1 t (nsec) 2 3 13
Example 2: Adder Circuit Cin Add Add1 Add2 Add14 Add15 S S1 S2 S14 S15 Sum Output Voltage, Volts 4. 2. Cin S1 S1. 5 1 Time, ns 3 2 4 6 5 S15 How to Cope with Glitching? F 1 1 F 2 2 F 3 F 1 F 2 1 1 F 3 Equalize Lengths of Timing Paths Through Design 14
Example: Carry Ripple versus Carry Lookahead A F A 1 A 2 A 3 A 4 A 5 A 6 A 7 Ripple A A 1 A 2 A 3 A 4 A 5 A 6 A 7 F Lookahead Example 1: Additions 15
Example 2: Multiplications Gate-Level Tradeoffs for Power Factoring Structuring Buffer insertion/deletion Don t care optimization Technology mapping Sizing Pin assignment 16
Factoring Idea: Remove common expressions to reduce capacitance Caveat: This may increase activity! Logic Restructuring Logic restructuring to minimize spurious transitions Buffer insertion for path balancing 17
Technology Mapping a b c d slack=1 Larger gates reduce capacitance, but are slower Use Large or Small Gates Example: 6-input AND 18
Sequential Logic Optimization State encoding» seems to be of minimal impact in general Data encoding in data paths» e.g. use of sign-magnitude, one-hot, or redundant representations» mostly ad hoc Retiming for low power» registers can be strategically placed to reduce glitching, or to perform path balancing Clock gating Pre-computation Clock gating Requires careful skew control... 19
Pre-computation Inputs x i x n are not applied if pre-computing holds Other options: guarded evaluation set output directly Short Circuit Currents Vdd Vin Vout C L.15 I VDD (ma).1.5. 1. 2. 3. V in (V) 4. 5. 2
Short Circuit Currents - Unloaded Impact of rise/fall times on short-circuit currents VDD VDD ISC ISC IMAX Vin CL Vout Vin CL Vout Large capacitive load Small capacitive load 21
How to keep Short-Circuit Currents Low? Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Dominates over dynamic consumption Not a function of switching frequency 22
Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-Threshold Current Dominant Factor Sub-Threshold in MOS I D V T =.2 V T =.6 V GS Lower Bound on Threshold to Prevent Leakage 23
Subthreshold Leakage Component 1-2 1-3 1-4 I D, A 1-5 1-6 1-7 1-8 1-9 V T =.1V V T =.4 V VGS + - V DS =1V I D 1-1 1-11 1-12.1.2.3.4.5.6.7.8.9 1. V GS, V Leakage control is critical for low-voltage operation 24