EE290C Spring Motivation. Lecture 6: Link Performance Analysis. Elad Alon Dept. of EECS. Does eqn. above predict everything? EE290C Lecture 5 2

Similar documents
ECE 546 Lecture 23 Jitter Basics

Measuring Deterministic Jitter with a K28.5 Pattern and an Oscilloscope

Voltage-Controlled Oscillator (VCO)

Issues with sampling time and jitter in Annex 93A. Adam Healey IEEE P802.3bj Task Force May 2013

The first printing of this book was produced with a few minor printing errors. We apologize for any confusion this might cause you.

Statistical and System Transfer Function Based Method For Jitter and Noise Estimation In Communication Design and Test

Jitter Decomposition in Ring Oscillators

Motivation for CDR: Deserializer (1)

EE115C Winter 2017 Digital Electronic Circuits. Lecture 19: Timing Analysis

Method for analytically calculating BER (bit error rate) in presence of non-linearity. Gaurav Malhotra Xilinx

Accurate Statistical Analysis of High-Speed Links with PAM-4 Modulation

RADIO SYSTEMS ETIN15. Lecture no: Equalization. Ove Edfors, Department of Electrical and Information Technology

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Predicting BER to Very Low Probabilities

Square Root Raised Cosine Filter

Presenters. Time Domain and Statistical Model Development, Simulation and Correlation Methods for High Speed SerDes

ECE 598 JS Lecture 17 Jitter

10GBASE-KR Transmitter Compliance Methodology Proposal. Robert Brink Agere Systems May 13, 2005

Data Converter Fundamentals

Preliminary Studies on DFE Error Propagation, Precoding, and their Impact on KP4 FEC Performance for PAM4 Signaling Systems

Understanding Data Sheet Jitter Specifications for Cypress Timing Products

Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM

The Linear-Feedback Shift Register

Study on Measurement Method of Clock Jitter

Here represents the impulse (or delta) function. is an diagonal matrix of intensities, and is an diagonal matrix of intensities.

Weiyao Lin. Shanghai Jiao Tong University. Chapter 5: Digital Transmission through Baseband slchannels Textbook: Ch

On Modern and Historical Short-Term Frequency Stability Metrics for Frequency Sources

Signal Design for Band-Limited Channels

Digital Band-pass Modulation PROF. MICHAEL TSAI 2011/11/10

EECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders

Principles of Communications

Similarities of PMD and DMD for 10Gbps Equalization

Oversampling Converters

EE5713 : Advanced Digital Communications

Q. 1 Q. 25 carry one mark each.

ADAPTIVE EQUALIZATION AT MULTI-GHZ DATARATES

Roundoff Noise in Digital Feedback Control Systems

MATHEMATICAL TOOLS FOR DIGITAL TRANSMISSION ANALYSIS

Designing Sequential Logic Circuits

that efficiently utilizes the total available channel bandwidth W.

IEEE 802.3ap Task Force Ottawa Sept 27-29, 2004

Accurate Fourier Analysis for Circuit Simulators

Principles of Communications Lecture 8: Baseband Communication Systems. Chih-Wei Liu 劉志尉 National Chiao Tung University

DesignCon 2008 EDA365. Modeling a Phase Interpolator as a Delta-Sigma Converter. Andy Martwick

Tracking of Spread Spectrum Signals

R. Garello. Tutorial on digital modulations - Part 9b m-pam [ ] 2

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-

DDR4 Board Design and Signal Integrity Verification Challenges

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003

Iterative Timing Recovery

GMU, ECE 680 Physical VLSI Design 1

Lecture 27 Frequency Response 2

D/A Converters. D/A Examples

The Accuracy of Jitter Measurements

Digital Baseband Systems. Reference: Digital Communications John G. Proakis

Optoelectronic Applications. Injection Locked Oscillators. Injection Locked Oscillators. Q 2, ω 2. Q 1, ω 1

A Statistical Study of the Effectiveness of BIST Jitter Measurement Techniques

Integrated Circuits for Digital Communications

EE194-EE290C. 28 nm SoC for IoT. Acknowledgement: Wayne Stark EE455 Lecture Notes, University of Michigan

Total Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method. White Paper

a_n x^(n) a_0 x = 0 with initial conditions x(0) =... = x^(n-2)(0) = 0, x^(n-1)(0) = 1/a_n.

Digital Communications

Linear Optimum Filtering: Statement

Leistungsfähigkeit von elektronischen Entzerrer in hochbitratigen optischen Übertragungsystemen. S. Otte, W. Rosenkranz. chair for communications,

ELEG 3124 SYSTEMS AND SIGNALS Ch. 5 Fourier Transform

EE241 - Spring 2006 Advanced Digital Integrated Circuits

EE 505 Lecture 10. Spectral Characterization. Part 2 of 2

Xarxes de distribució del senyal de. interferència electromagnètica, consum, soroll de conmutació.

Convolution and Linear Systems

UCSD ECE153 Handout #40 Prof. Young-Han Kim Thursday, May 29, Homework Set #8 Due: Thursday, June 5, 2011

Pre Silicon to Post Silicon Overview. Adam Norman Intel Corp. PCCG

EECS150 - Digital Design Lecture 16 Counters. Announcements

Data Detection for Controlled ISI. h(nt) = 1 for n=0,1 and zero otherwise.

Advanced Testing. EE5375 ADD II Prof. MacDonald

SIMON FRASER UNIVERSITY School of Engineering Science ENSC 380 Linear Systems. Solutions to Assignment 2 Spring 2000

EEE 421 VLSI Circuits

EE303: Communication Systems

Behavior of Phase-Locked Loops

Fading Statistical description of the wireless channel

ELEC E7210: Communication Theory. Lecture 4: Equalization

= 4. e t/a dt (2) = 4ae t/a. = 4a a = 1 4. (4) + a 2 e +j2πft 2

Ranging detection algorithm for indoor UWB channels

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lecture 2. Capacity of the Gaussian channel

ECE Branch GATE Paper The order of the differential equation + + = is (A) 1 (B) 2

EE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling

24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL

Pulse Shaping and ISI (Proakis: chapter 10.1, 10.3) EEE3012 Spring 2018

Approximation Approach for Timing Jitter Characterization in Circuit Simulators

EE 230 Lecture 40. Data Converters. Amplitude Quantization. Quantization Noise

Accurate GHz channel simulation and statistical analysis for SSE(Solution Space Exploration)

Fundamentals of PLLs (III)

The PUMA method applied to the measures carried out by using a PC-based measurement instrument. Ciro Spataro

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Imperfect Sampling Moments and Average SINR

EE4512 Analog and Digital Communications Chapter 4. Chapter 4 Receiver Design

Solutions to Selected Problems

A New Approach for Computation of Timing Jitter in Phase Locked Loops

Example: Bipolar NRZ (non-return-to-zero) signaling

ENGR352 Problem Set 02

Transcription:

EE29C Spring 2 Lecture 6: Link Performance Analysis Elad Alon Dept. of EECS Motivation V in, ampl Voff BER = 2 erfc 2σ noise Does eqn. above predict everything? EE29C Lecture 5 2

Traditional Approach Borrowed from computer systems Built to be error free Worst-case analysis Voltage/Time (VT) Budget Also called link budget (especially in wireless) Key: separate random vs. deterministic error sources EE29C Lecture 5 3 Voltage Budget Example EE29C Lecture 5 4

Voltage Budget Example EE29C Lecture 5 5 Timing Budget: Jitter Definitions Like voltage need to separate deterministic (bounded) from random (unbounded) Total jitter (TJ) = Deterministic (DJ) + random (RJ) DJ is measured as peak-to-peak, added linearly RJ is measured as rms For BER = -2, peak-to-peak RJ is 4*RMS value Don t forget that jitter gets filtered too E.g., source synchronous, CDR EE29C Lecture 5 6

Jitter Tolerance Mask Jitter Amplitude (UI) 9. 8.5 8. 7.5 7. 6.5 6. 5.5 5. 4.5 4. 3.5 3. 2.5 2..5..5. CDR Tolerance & XAUI Sinusoidal Jitter Tolerance Mask.UI XAUI Sinusoidal Jitter Mask.875MHz. 22KHz.... Jitter Frequency (MHz) XAUI Mask LV at Vtt-Rx=V & 3.25Gbps Specifies amplitude of sinusoidal jitter (SJ) vs. frequency for which link must maintain BER spec Mask drives CDR loop filter characteristics.ui 2 MHz EE29C Lecture 5 7 Jitter in Source Synchronous Systems EE29C Lecture 5 8

Jitter in Source Synchronous Systems EE29C Lecture 5 9 Issues with Traditional Approach Is worst-case realistic? What if you had taps of residual ISI? Can you really treat timing and voltage noise completely separately? EE29C Lecture 5

Communications Approach Model small deterministic errors as Gaussian Find σ, multiply it to get peak-to-peak value at given BER Works well at low BER (e-3), but EE29C Lecture 5 Issues with Communications Approach log probability [cdf] Cumulative ISI distribution -2-4 -6-8 - 4mV error @ - 25% of eye height 25 5 75 residual ISI [mv] log Steady-State Phase Probability 8 2 4 6 8 phase count Gaussian model breaks at lower probabilities -2-4 -6-8 - CDR phase distribution 9% T symbol 4% T symbol error @ - EE29C Lecture 5 2

A More Modern Approach Use direct noise and ISI statistics Don t treat timing noise separately Integrate with voltage noise sources I.e., need to map from time to voltage Ref: V. Stojanovic, Ph.D. thesis EE29C Lecture 5 3 Residual ISI Generally can t correct for all ISI Equalizers are finite length Even with infinite equalizers, the coefficients are quantized And you may not be able to estimate coefficient values perfectly Need to find distribution of this residual ISI EE29C Lecture 5 4

Generating ISI Distributions voltage [mv] Equalized pulse response 2 5 - -3-2 - 2 sample # probability [pmf] probability [pmf].75.5.25.75.5.25 Convolution -5 [mv] 5 probability [pmf] ISI distribution.75.5.25-25 -5 5 25 voltage [mv] - [mv] EE29C Lecture 5 5 Real ISI Dist.: 5-tap FIR probability distribution of residual ISI.4.3.2. probability distribution of residual ISI.6.2.8.4-6 -4-2 2 4 6 voltage [mv] Data sample distribution -5 - -5 5 5 voltage [mv] Edge sample distribution EE29C Lecture 5 6

Effect of Timing Noise Need to map from time to voltage Voltage noise when receiver clock is off Jittered sampling Ideal sampling Voltage noise Effect depends on jitter magnitude, input sequence, and channel EE29C Lecture 5 7 Effect of Jitter: Decomposition ε k kt b k ε k+ ( k +)T ideal noise Decompose output into ideal + noise Jitter is pulse at front and end of symbol Width of pulse set by jitter magnitude 2 kt ε k b k b k + ( k +)T ε k+ b k EE29C Lecture 5 8

Converting to Voltage bkε k+ ε k b k ε k+ b k b ε k k Variable width pulses annoying to deal with Approximate noise pulses with deltas of same area Channel is low-pass and will filter them anyways EE29C Lecture 5 9 Jitter Propagation Model a k precoder b pulse response ideal k w p( jt) ISI x k + x k â k n vdd PLL H jit (s) noise Channel bandwidth matters jit ISI RX x ( kt + φ + ε ) = φ ) If h(t/2) is small, jitter voltage noise is small EE29C Lecture 5 2 x RX ε k n in T k h jt + 2 εk, k+ impulse RX response sbe i k b k j p ( jt + i j = sbs sbe jitter RX T x ( kt + φi + εk ) = bk j h( jt + + φi ) k k j i k εk+ j j= sbs 2 2 RX T RX ( ε ε ) h( jt + φ )( ε )

Implications Jitter High frequency (period) jitter is bad Changes the energy (area) of the symbol) Uncorrelated noise sources add up Low frequency jitter isn t as bad Just shifts waveform Correlated noise sources partially cancel ε k Rx RX jitter Shifts sequence same as low f jitter EE29C Lecture 5 2 ε k Rx Implications For same source jitter (white) Noise from jitter larger than RX jitter jitter enhanced by channel Bandwidth of jitter sets final magnitude Like any other white noise source Power spectral density [dbv] -3-4 -5-6 Source white jitter Noise from Tx jitter Noise from Rx jitter.5.5 2 2.5 3 frequency [GHz] EE29C Lecture 5 22

Including the CDR Slicer d n deserializer RX dataout d n PD e n data Clk edge Clk Phase control Phase mixer PLL ref Clk d n- e n (late) Need jitter on actual sampling clock Not just jitter from source, PLL EE29C Lecture 5 23 CDR Model Model as a state machine Current phase position is the state Transitions caused by early/late signals Probability.8.6.4.2 Accumulate-reset filter, length 4 p-early p-up p-dn p-no-valid transitions p-late p-hold 5 5 2 25 Phase count On average move to right position But probability of incorrect transition not small EE29C Lecture 5 24

What You Really Care About Final steady-state probability of being in each phase position (state) p dni, p hold, i Probability.8.6 Accumulate-reset filter, length 4 p-up p-dn p-no-valid transitions φ p up, i φ φ i i φ i + φl.4.2 p-early p-late p-hold 5 5 2 25 Phase count Can find using Markov model Fancy way of saying that you iteratively apply the transition probabilities EE29C Lecture 5 25 Result: CDR Phase PDF log Steady-State Probability -5 - -5 5 5 2 25 Phase Count This is the jitter distribution (With nominal phase subtracted out) EE29C Lecture 5 26

ISI and CDR Distributions voltage [mv] 3 2-2PAM - lin. eq -5 - -5-2 -2-25 -3 5 6 7 8 9 time [ps] Vertical slice: ISI distribution @ given time Horizontal weight: CDR phase distribution -3 EE29C Lecture 5 27 Putting It All Together: BER Contours 5 5 tap Tx Eq 5 tap Tx Eq + tap DFE 5-5 -5 margin [mv] 5-5 - -5-2 margin [mv] 5-5 - -5-2 - -25 - -25-5 2 4 6 8 2 4 6 time [ps] Voltage margin @ given BER: -3-5 2 4 6 8 2 4 6 time [ps] Distance from probability contour to threshold () -3 EE29C Lecture 5 28

Model and Measurements -2 log(ber) -4-6 -8 - -2-4 8 6 4 2-2 -4-6 -8 Voltage Margin [mv] EE29C Lecture 5 29