Redution of Swithing Noise in Digitl CMOS Ciruits y Pin Swpping of Lirry Cells 1 Pilr Prr, Antonio Aost, nd Mnuel Vleni Instituto de Miroeletróni de Sevill-CNM / Universidd de Sevill Avd. Rein Meredes s/n, 41012-Sevill, SPAIN Phone: +34-95-505-66-66; Fx: +34-95-505-66-86; e-mil: ojim@imse.nm.es Astrt. The ojetive of this pper is to explore the ppliility of very speifi design tehnique t gte-level to hieve redution of swithing noise in onventionl CMOS digitl iruits. The proposed tehnique optimies swithing noise mintining opertion speed, power onsumption nd trnsistor ount. Bsilly, we will show how the seletion of the suited pin in gte for implementing logi funtion, n ring importnt dvntges in terms of swithing noise redution. The hrterition of some CMOS 0.35 µm lirry ell shows different ehvior regrding swithing noise depending on wht trnsitions in whih input pin tkes ple. This hs een used s the sis for noise optimition methodology, verified through some design exmples showing the noise redution produed y the use of the proposed tehnique. 1 Introdution In modern mixed-signl nlog-digitl Integrted Ciruits, swithing noise is eoming limiting ftor, sine it limits the performne of the glol system [1-3]. Within onventionl digitl design methodologies, some tivities n e onsidered to redue swithing noise. Bsilly, swithing of digitl gtes injets rriers through the sustrte, eing responsile of the resistive-pitive oupling (Fig 1). Also, pkge prsitis indue noise in the on-hip supply-ground plnes (Fig 1). Sine these prolem limit the performne of the nlog prt, nd hene, the whole system, is importnt, on one hnd, to mesure swithing noise, monitoring the mximum -pek vlue- of dynmi urrent provided y the supply soure (i VDD ), tht is proportionl to the rrier injetion [1], [3]. On the other hnd, the use of noise redution tehniques in the nlog domin is importnt to llevite the influene of swithing noise [2]. Conerning digitl design methodologies, some low-swithing-noise digitl CMOS fmilies hve een reported: Current Steering Logi [4], Folded Soure-Coupled Logi [1] nd NMOS Current-Blned Logi [5], mong others. These urrent-mode strutures work with supply urrent lmost onstnt, thus reduing vrition in supply ur- 1. This work hs een sponsored y the Spnish MCYT TIC2000-1350 MODEL Projet.
Redution of Swithing Noise in Digitl CMOS Ciruits 9.3.2 Noise genertion re Noise sensile re R 1 R ) R2 _on_hip in Gnd Lpin i VDD in Lpin PMOS NMOS out C vdd C gnd out Gnd Gnd Gnd_on_hip i VDD 1mA _on_hip 0 C vdd _on_hip Lpin PMOS i VDD in out Gnd -50mV Lpin NMOS C gnd t Gnd_on_hip 1 ns ) Figure 1 ) Crrier injetion through the sustrte: resistive-pitive oupling. ) Pkge prsitis indue noise in the on-hip supply-ground plnes rent nd, hene, swithing noise. However, stti power onsumption is the min penlty of suh strutures, mking them strongly unsuited for low-power pplitions. Thus, lrge logi iruits should e implemented with onventionl CMOS design styles, eing interesting the seletion of the most suited CMOS digitl struture for n speifi low-noise, low-voltge nd low-power digitl pplition. When designing lrge logi iruit using modern CMOS methodologies, topdown pproh is ommonly used. A high-level desription like VHDL or Verilog serves s input of synthesis tools, generting n shemti desription of the iruit, or diretly the lyout. There re some wys of swithing noise optimition onsidering the level of desription, like when optimiing in power, speed or re. In generl, tions t system level n ring lot of dvntges, for instne lterntive rhiteturl llotion nd sheduling [3], nd the right hoie of the loking sheme [6], ut the provided solutions re often very dependent of the speifi system. On the other hnd, tions t lowest levels, like lyout or trnsistor level [1], [3-5], [7], re very fr from the stndrd digitl designer. In this wy, optimition t gte level n offer the
9.3.3 P. Prr et l. possiility of otining redution of swithing noise t low ost, if suited proedures like the one presented in this pper is used. The present ommunition inludes n speifi solution t gte-level, tht optimie swithing noise mintining opertion speed, power onsumption nd trnsistor ount. Bsilly, we will show how the seletion of the suited pin in gte for implementing logil funtion, n ring importnt dvntges in terms of swithing noise redution. The orgnition of the ommunition is s follows: Setion 2 shows the hrterition of some lirry ells onerning swithing noise nd input pins, s well s some onsidertions out mesuring swithing noise. Setion 3 inludes the design methodology oriented to low swithing noise genertion y pin swpping. Setion 4 summries some design exmples, showing the dvntges of the proposed methodology. Finlly, Setion 5 presents the min onlusions. 2 Chrterition of Lirry Cells for Swithing Noise Mesurement As n indiret mesurement of the swithing noise, the urrent supply pek hs een onsidered. Tking the shemti t the gte-level desription of the iruit under hrterition, we hve performed omplete eletril simultion (using SPECTRE) of multiple-input gtes, inluded in the AMS stndrd 0.35 µm CMOS lirry [8]. We hve onsidered, s interest prmeters, vritions in urrent supply due to input slope nd input seletion. Although it is not n exhustive hrterition, with these prmeter under onsidertion we wnt to demonstrte tht the onsidered effets hve lot of influene on supply urrent, nd hene on noise genertion, in suh wy tht they n led to swithing noise redution, if suited optimition proedures of pin swpping re tken into ount [9]. For the ske of simpliity, only results for the 3-input NAND, 2-input XOR nd 2-input OR gtes re shown. 2.1 Influene of input seletion on swithing-noise genertion SPECTRE simultions of multiple-input gtes show tht noise generted y swithing inputs depends on the speifi input onsidered, due to symmetry in the implementtion of gtes (input pitne, sustrte effet, lyout, et). For instne, let us onsider the 3-input NAND gte of Fig 2 nd the swithing noise mesurements in the Tle of Fig 2. As illustrtive dt, for the trnsition : 111 -> 110, : 0->1, pek in supply urrent is 339.7 µa, while for trnsition : 111 -> 011, : 0->1, pek in supply urrent is 271.7 µa. Vrition is round 25%, eing the logi opertion the sme in oth ses. Equivlent results n e otined for the 2-input XOR (Fig 2 nd tle in Fig 2d) nd 2-input OR (Fig 2e nd tle in Fig 2f) gtes. 2.2 Influene of the slope of input wveforms on swithing noise genertion Let us onsider the iruit in Fig 3, ontining the gtes of Fig 2. The influene of input slope hs een inluded y hnging the drive-strength of the input inverters. Tles in
Redution of Swithing Noise in Digitl CMOS Ciruits 9.3.4 Trnsition in: (=11) (=11) (=11) rises 271.7 314.5 339.7 flls 293.0 293.2 299.5 ) ) Trnsition in: (=0) (=0) rises 425.8 370.8 flls 366.6 351.2 ) d) Trnsition in: (=0) (=0) rises 353.8 388.6 flls 288.6 303.6 e) f) Figure 2 ) 3-input NAND, ) 2-input XOR nd e) 2-input OR gtes. ), d) nd f) Pek in supply urrent produed y isolted trnsitions in respetive inputs Fig 3 inlude the pek of supply urrent orresponding to the NAND, XOR nd OR gtes when drive-strength of inverters is sled y 1 nd 8. Dt indite tht noise inreses with input slope inrements, even mking tht, for the NAND gte, the originlly less noisy input for drive-strength 1 (out 25% less noise in pin ) eomes the most noisy (out 8% more noise) for drive-strength 8, due to higher input slope. 3 Low Swithing Noise Oriented Design Methodology The results presented in lst Setion lerly show how the ehvior of lirry ells regrding swithing noise strongly depends on the pin seletion. To tke dvntge of this dependene, our min purpose is to optimie given gte-level shemti to redue the pek of urrent supply vi pin swpping. For n speifi funtionlity, the suited mpping of suh funtionlity on hrdwre tking into ount the hoie of onnetivity in ells, s well s dynmi spets relted to wveforms nd swithing tivity re of importnt onern when designing digitl iruits for low-noise pplitions. In this wy, our design tem is urrently involved in developing forml optimition methodologies nd lgorithms le to detet situtions worthy of optimition nd to perform suh op-
9.3.5 P. Prr et l. Drive-Strength x1 x8 ) timition. The proposed tehniques, n e onsidered s guidelines for the design for low-noise prdigm. Furthermore, other stti nd dynmi onsidertions, mny of them depending on swithing tivity, should e tken into ount s, for instne, the influene of supply voltge, glithes, et., nd will e lso onsidered in future work. Fig 4 shows glol representtion of the flow for the proposed optimition methodology. The strting point is gte-level shemti otined from either silion ompiler or n humn designer (y hnd). Suh shemti is firstly nlyed to otin informtion out onnetivity, fnin nd fnout of gtes, in order to estimte the input slope of wveforms. Suh informtion will e used for pin swpping optimition. Logi simultion provides us dditionl informtion out simultneous swithing tivity in nodes, very importnt sine simultneous trnsitions re the min ontriution to inresing swithing noise. The nlysis of the otined informtion is used to detet the situtions tht re worthy of optimition, through heking the nodes with higher tivity nd mpping suh nodes to the less noisy pins in the lirry ells. The estimtion of noise redution is performed through the evlution of the opertion ondition, nd the omprison with the noise models of the ells. One the pins re swpped if im Trnsition in: (=11) (=11) (=11) rises 271.7 / 445 314.5/430.6 339.7/411.9 flls 293 / 372.2 293.2/355.2 299.5/359.7 ) Drive-Strength x1 x8 ) Trnsition in: (=0) (=0) rises 425.8 / 448.2 370.8 / 408.5 flls 366.6 / 1169 351.2 / 1047 d) Trnsition in: (=0) (=0) rises 353.8 / 371.2 388.6 / 398.3 flls 288.6 / 516.3 303.6 / 641.3 Drive-Strength x1 x8 e) f) Figure 3 ) Ciruit using 3-input NAND gte. ) Pek in supply urrent when the inputs swith nd when drive-strength of input inverters re x1 nd x8 (x1 / x8). )-d) The sme for 2-input XOR gte. e)-f) The sme for 2-input OR gte
Redution of Swithing Noise in Digitl CMOS Ciruits 9.3.6 Humn Designer Silion Compiler Shemti Logi Simultion Stti Anlysis Ativity Mp Lirry Models Pin Swpping Simultneous Trnsitions Input Slope Fnin Fnout Optimition Noise Evlution Eletril or Swith-level Simultion Optimied Shemti Figure 4 Proposed low swithing noise optimition methodology. The utomtion of this proedure is urrently under development provement is expeted, the glol noise is evluted through eletril or swith-level simultion (in our se Spetre nd Mh-PA hve een used). The itertion in the optimition proess yields in finl shemti optimied for low swithing noise genertion. Let us show now two simple nd illustrtive exmples: Exmple 1: From the results presented in Setion 2 for the 3-input NAND gte, onneting the input with higher tivity to pin yields in lol redution of swithing noise. The exmple of Fig 5 shows two possile logi implementtions of the omintionl funtion =uvw+x +y using two 3-input NAND gtes. Supposing tht ll inputs (u,v,w,x,y) swith with the sme proility, node t hs less swithing proility thn x nd y, nd hene, less noise is generted if t is onneted to pin of the output NAND thn if onneted to pin. Vrition in pek of supply urrent is out 5% for simultion with 200 rndom ptterns. Exmple 2: Simultion dt presented in Setion 2 indited tht noise inreses with input slope. In the exmple of Fig 6, two speed optimied implementtions of the u v w x y t u v w x y t Figure 5 Two equivlent implementtions, with 3-input NAND gtes, of the funtion =uvw+x +y, ut the left produing 5% more noise
9.3.7 P. Prr et l. u v w x8 x x8 y x8 t u v w x8 x x8 y x8 t Figure 6 Implementtions of =uvw+x +y using 3-input NAND gtes funtion =uvw+x +y using 3-input NAND gtes re onsidered. In the left implementtion, node t hs less trnsitions nd the less noisy implementtion onnets suh node to pin of NAND gte (see Tle in Fig 3 for drive-strength x8). However, if node t hs dditionl onnetions, the pitne of node t inreses, nd input slope dereses. In suh se, the less noisy solution is the onnetion of node t to pin, s shown in the right of Fig 6. The redution of pek in supply urrent is out 3% in the left se nd 8% in the right se. Note tht proposed solutions in oth exmples do not modify the hrdwre resoures involved, thus the redution of swithing noise is otined without re ost. 4 Demonstrtor Exmple The proposed methodology hs een pplied to more omplited exmple: modulr implementtion of n unsigned-to-signed dt onverter. The output is given in two somplement nd one s-omplement formts, depending on the vlue of signl. The omintionl funtion implemented is represented in eq. (1): i = XOR( i, i 1 +... + 1 + 0 + ) (1) If =1, eq. (1) is onverted into eq. (2), eing the one s-omplement of input : i = i If =0, eq. (1) is onverted into eq. (3), eing the two s-omplement of input : i = XOR( i, i 1 +... + 1 + 0 ) (3) A modulr representtion of suh funtionlity is shown in Fig 7. It is ler tht mximum prllelism is in opertion of XOR gtes, swithing the output s result of hnges in, swithing ll the XOR gtes (lmost) simultneously. This simultneous (2)
Redution of Swithing Noise in Digitl CMOS Ciruits 9.3.8 k+1 k k-1 1 0 k k-1 1 0 k+1 Figure 7 Modulr implementtion of n unsigned-to-signed dt onverter. If =0 (1), the output is given in two s(one s)-omplement formt hnge is the min ontriution to swithing noise. Otherwise, the trnsmission of the first i =1 to the most signifitive ells, through the OR hin, mkes the trnsitions onseutive in time. Itertion in the proedure of Fig 4, hs given the following results: When =1, the hoie of pin input in XOR gtes is ruil. Sine pin onneted to i is the more proly to hnge (50%), i should e onneted to less noisy pin in XOR gte ( in the hrteried lirry ell). On the other hnd, when =0, the outputs of the OR gtes hve less proility of hnge (25%), nd gin, the less noisy input pin of XOR gtes should e onneted to i signls. Sine fnout of OR gtes (2) is the sme of gtes loded y inputs i, similr slope is expeted for oth inputs of XOR gtes, thus there will not e signifint dependene of noise on input slope. As we hve lredy disussed, the OR gtes ontriution to the totl noise of the dt sign onverter is less signifint thn XORs, however, suited hoie in input seletion n ontriute to mke less noisy the dt omplementer. One of the inputs in eh OR gte is onneted to the dt it i while the other input is fed y the preedent stge OR gte. Although the pin onneted to i is the more proly to hnge, the only hnge tht ffets the vlue of the OR gte output is the hnge 0->1 nd this is trnsmitted long the OR pth through the other pin, hene, for noise redution we should onnet the most noisy pin to i. As summry of simultion results, Tle 1 inludes the dt otined for three different possiilities of pin swpping in gtes of the unsigned-to-signed onverter of Fig 7. The verge of peks in supply urrent, s well s the vrine, mesured through the pplition of vrile-length (from 200 to 2000) rndom ptterns hve een onsidered s indiret mesurement of swithing noise. For eh se, three opertion modes hve een onsidered, one s omplement onversion (=0), two s omplement onversion (=1), nd rndom opertion ( rnd). The energy onsumption per trnsition in eh of them hs lso een omputed. Simultion tool is MACH PA, from Mentor Grphis. The opertion with =0 (two s omplement) provides the most noisy solutions. Tle 1 lso shows tht se i -> (XOR), i -> (OR) is the est from the point of view of noise, eing the worst se when i -> (XOR) nd i -> (OR), s it ws expeted
9.3.9 P. Prr et l. Tle 1: Pek of supply urrent (ma) s noise mesurement nd energy onsumption per trnsition (fj) for the pin seletion nd for onverter length 8-it 16-it 32-it energy noise energy noise energy noise i->(xor) i -> (OR) i->(xor) i -> (OR) = 0 537 1.336±0.594 765 2.264±0.654 1194 4.086±1.029 = 1 224 1.005±0.391 451 1.997±0.532 887 3.845±0.960 rnd 414 1.291±0.508 635 2.220±0.617 1074 4.097±1.002 = 0 566 1.432±0.546 840 2.557±0.658 1402 4.725±1.123 = 1 266 1.160±0.425 551 2.313±0.564 1081 4.485±1.123 rnd 458 1.419±0.495 733 2.548±0.632 1297 4.717±1.081 = 0 562 1.478±0.545 811 2.653±0.680 1462 4.996±1.181 i ->(XOR) i -> (OR) = 1 263 1.230±0.448 545 2.480±0.605 1230 4.835±1.129 rnd 486 1.480±0.496 741 2.648±0.689 1397 5.030±1.157 from the ove resoning, nd from dt of Fig 2. We n see tht noise inrese with the length of the sign onverter, ut if we ompre with the worst se ( i -> (XOR), i -> (OR)), the gin in noise is lso inresing, out 12.7% for the 8-it, 16.2% for the 16-it nd 18.5% for the 32-it version, hving onsidered rndom opertion for perentge omputtion. Also it n e notied tht for given length, for exmple 8 its, the gin in noise is different for eh opertion mode, eing 9.6% for =0, 18.3% for =1 nd 12.7% for rndom. An dditionl disussion should e mde in order to hek if deresing noise mens deresing performnes. Tle 1 shows tht se i -> (XOR), i -> (OR) is the est from the point of view of noise nd lso of energy, so the improvement in noise tht we get y pin swpping does not ffet the performne in power onsumption. On the other hnd, onerning speed degrdtion, the pin swpping in gtes ffet the performne of the dt sign onverter. For the XOR gte, the dely through pins nd is similr when the other input is 1, (vrying etween 110 nd 115 ps when output rises nd etween 120 nd 113 ps when output flls), however, when the onstnt input is 0 the dely through pin is higher thn through pin (vrying etween 263 nd 203 ps when output rises nd etween 275 nd 248 ps when output flls). As in the less noisy omplementer we mke i -> (XOR) nd i hs 50% proility of hnge, we re mking the worst seletion for dely riteri. Although this n seem loss in performne, the XOR dely does not ffet the opertion frequeny for the dt sign onverter eing the OR hin dely the limiting ftor. If we ompute the mximum dely se for the less noisy nd for the more noisy dt sign onverters, we found different results sine the pin seletion in OR gtes is the ontrry for oth. In the se of the more noisy
Redution of Swithing Noise in Digitl CMOS Ciruits 9.3.10 iruit we find higher delys: 3360 ps for the 8-it, 6992 ps for the 16-it nd 14256 ps for the 32-it omplementer, while for the less noisy iruit we find 2900 ps for the 8- it, 6052 ps for the 16-it nd 11428 ps for the 32-it. This is euse, in the OR gte, the dely through pin is greter thn through pin, nd in the less noisy dt sign onverter we mke -> (OR), so we re mking the est seletion for dely riteri. 5 Conlusions In the mixed-signl ommunity is widely epted the importne of deresing swithing noise to improve the performne of the A/D integrted iruits. This ommunition nlyes nd presents some solutions to redue the swithing noise in onventionl CMOS digitl designs. Suh tions tke ple t gte-level, very lose to most of digitl designer nd simply onsists in finding equivlent iruits nd strutures with less peks in supply urrent. More speifilly, design methodology sed in pin swpping hs een proposed, lso onsidering the effets of input slope in noise generted. The proposed tehniques hve een vlidted through seleted exmples, showing the improvement in terms of swithing noise. It hs lso een demonstrted tht deresing swithing noise does not neessrily mens degrdtion of performnes. Future work will e devoted to utomte the optimition of iruit t gte level onsidering the swithing noise redution s trget. Finlly, n dditionl ojetive is the design of lirry ell oriented towrds low swithing noise genertion to e used in mixed-signl designs. Referenes 1. D.J. Allstot, S-H. Chee nd M. Shrivstw, Folded Soure-Coupled Logi vs. CMOS Stti Logi for Low-Noise Mixed-Signl ICs, IEEE Trns. Ciruits nd Systems I, 40, pp. 553-563, Sept. 1993. 2. Y. Tsividis, Mixed Anlog-Digitl VLSI Design nd Tehnology. MGrw-Hill, 1995. 3. X. Argonès, J. L. Gonále nd A. Ruio, Anlysis nd Solutions for Swithing Noise Coupling in Mixed-Signl ICs. Kluwer Ademi Pulishers, 1999. 4. H-T. Ng nd D.J. Allstot, CMOS Current Steering Logi for Low-Voltge Mixed-Signl Integrted Ciruit, IEEE Trns. VLSI Systems, 5, pp. 301-308, Sept. 1997. 5. E. Aluquerque, J. Fernndes nd M. Silv, NMOS Current-Blned Logi, Eletronis Letters, 32, pp. 997-998, My 1996. 6. A.J. Aost, R. Jiméne, J., M. J. Jun, Bellido, nd M. Vleni, Influene of loking strtegies on the design of low swithing-noise digitl nd mixed-signl VLSI iruits, in 10th PATMOS, pp. 316-326, Göttingen, Sept. 2000. 7. R. Jiméne, A.J. Aost, J. Jun, M.J. Bellido nd M. Vleni, Study nd Anlysis of Low- Voltge Low-Power CMOS Logi Fmilies for Redution of Swithing Noise, in 9th PAT- MOS, pp. 377-386, Kos Islnd, Otoer 1999. 8. Dtsheets of 0.35 µm Stndrd Cells, Austri Miro Systems in http://www.msint.om/ produts/tehnology/index_035.html 9. A.J. Aost, P. Prr, J. Jun, M. Vleni, nd R. Jiméne, Redution of Swithing Noise in Low-Power CMOS Digitl Ciruits y Gte-level Optimition, Interntionl Workshop on Logi nd Synthesis, pp.101-106. June 2001.